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[Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from features |
Date: |
Sat, 15 Sep 2018 09:17:32 -0700 |
Unlike the other id_sar registers, these contain post-v8.0 features
that are not included with any existing cpu models. They would be
enabled by -cpu max when we enable them for system mode.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3c6ddd6532..c227044946 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -926,6 +926,49 @@ static uint32_t resolve_id_isar4(CPUARMState *env)
return ret;
}
+static uint32_t resolve_id_isar5(CPUARMState *env)
+{
+ uint32_t ret = 0;
+
+ /* SEVL -- we always implement as NOP. */
+ /* AES */
+ if (arm_feature(env, ARM_FEATURE_V8_PMULL)) {
+ ret = deposit32(ret, 4, 4, 2);
+ } else if (arm_feature(env, ARM_FEATURE_V8_AES)) {
+ ret = deposit32(ret, 4, 4, 1);
+ }
+ if (arm_feature(env, ARM_FEATURE_V8_SHA1)) {
+ ret = deposit32(ret, 8, 4, 1); /* SHA1 */
+ }
+ if (arm_feature(env, ARM_FEATURE_V8_SHA256)) {
+ ret = deposit32(ret, 12, 4, 1); /* SHA2 */
+ }
+ if (arm_feature(env, ARM_FEATURE_CRC)) {
+ ret = deposit32(ret, 16, 4, 1); /* CRC32 */
+ }
+ if (arm_feature(env, ARM_FEATURE_V8_RDM)) {
+ ret = deposit32(ret, 24, 4, 1); /* RDM */
+ }
+ if (arm_feature(env, ARM_FEATURE_V8_FCMA)) {
+ ret = deposit32(ret, 28, 4, 1); /* VCMA */
+ }
+
+ return ret;
+}
+
+static uint32_t resolve_id_isar6(CPUARMState *env)
+{
+ uint32_t ret = 0;
+
+ /* JSCVT -- not implemented yet */
+ /* FHM -- not implemented yet */
+ if (arm_feature(env, ARM_FEATURE_V8_DOTPROD)) {
+ ret = deposit32(ret, 4, 4, 1); /* DP */
+ }
+
+ return ret;
+}
+
static void resolve_id_regs(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -951,6 +994,9 @@ static void resolve_id_regs(ARMCPU *cpu)
cpu->id_isar4 = resolve_id_isar4(env);
/* Willfully ignore the SWP_frac field. */
g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, ==, orig & 0x0fffffff);
+
+ cpu->id_isar5 = resolve_id_isar5(env);
+ cpu->id_isar6 = resolve_id_isar6(env);
}
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
--
2.17.1
- [Qemu-devel] [PATCH 01/13] target/arm: Add ARM_FEATURE_SWP, (continued)
- [Qemu-devel] [PATCH 02/13] target/arm: Derive id_isar0 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 03/13] target/arm: Derive id_isar1 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 05/13] target/arm: Derive id_isar3 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 06/13] target/arm: Derive id_isar4 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 04/13] target/arm: Derive id_isar2 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 08/13] target/arm: Derive id_pfr0 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from features,
Richard Henderson <=
- [Qemu-devel] [PATCH 09/13] target/arm: Derive id_pfr1 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 10/13] target/arm: Derive id_aa64isar0 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 11/13] target/arm: Derive id_aa64isar1 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 13/13] target/arm: Remove assertions from resolve_id_regs, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 12/13] target/arm: Derive id_aa64pfr0 from features, Richard Henderson, 2018/09/15
- Re: [Qemu-devel] [RFC PATCH 00/13] target/arm: Derive cpu id regs from features, Alex Bennée, 2018/09/19