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Re: [Qemu-devel] [PATCH 1/3] aspeed/i2c: interrupts should be cleared by
From: |
Cédric Le Goater |
Subject: |
Re: [Qemu-devel] [PATCH 1/3] aspeed/i2c: interrupts should be cleared by software only |
Date: |
Tue, 25 Sep 2018 12:44:47 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 09/25/2018 12:15 PM, Peter Maydell wrote:
> On 25 September 2018 at 10:12, Cédric Le Goater <address@hidden> wrote:
>> On 09/25/2018 11:02 AM, Peter Maydell wrote:
>>> On 14 September 2018 at 07:35, Cédric Le Goater <address@hidden> wrote:
>>>> and the bus interrupt should be lowered when all interrupts have been
>>>> cleared. Also, the model does not implement correctly the RX_DONE bit
>>>> behavior which should be cleared to allow more data to be received.
>>>> Yet to be fixed.
>>>>
>>>> Signed-off-by: Cédric Le Goater <address@hidden>
>>>> ---
>>>> hw/i2c/aspeed_i2c.c | 21 +++++++++++++++++----
>>>> 1 file changed, 17 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
>>>> index c762c7366ad9..de6b08378675 100644
>>>> --- a/hw/i2c/aspeed_i2c.c
>>>> +++ b/hw/i2c/aspeed_i2c.c
>>>> @@ -52,6 +52,13 @@
>>>> #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control
>>>> #1 */
>>>> #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */
>>>> #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */
>>>> +
>>>> +#define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1:
>>>> addr2 */
>>>> +#define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30)
>>>> +/* bits[19-16] Reserved */
>>>> +
>>>> +/* All bits below are cleared by writing 1 */
>>>> +#define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15)
>>>> #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
>>>> #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
>>>> #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only
>>>> */
>>>> @@ -59,11 +66,16 @@
>>>> #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
>>>> #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
>>>> #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
>>>> -#define I2CD_INTR_SLAVE_MATCH (0x1 << 7) /* use RX_DONE */
>>>> +#define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */
>>>> #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
>>>> #define I2CD_INTR_ABNORMAL (0x1 << 5)
>>>> #define I2CD_INTR_NORMAL_STOP (0x1 << 4)
>>>> #define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
>>>> +
>>>> +/*
>>>> + * TODO: handle correctly I2CD_INTR_RX_DONE which needs to be cleared
>>>> + * to allow next data to be received.
>>>> + */
>>>> #define I2CD_INTR_RX_DONE (0x1 << 2)
>>>
>>> Is this TODO something different from the behaviour involving
>>> this RX_DONE bit which is fixed in patch 3 in this set ?
>>
>> no. It's the same but the TODO was not removed. I intended to do
>> so after a possible merge.
>
> OK. I'll fix up the commit message and drop the TODO message from
> this patch when I put the series into target-arm.next, if that's ok.
Sure.
Thanks,
C.
[Qemu-devel] [PATCH 2/3] aspeed/i2c: Handle receive command in separate function, Cédric Le Goater, 2018/09/14
[Qemu-devel] [PATCH 3/3] aspeed/i2c: Fix receive done interrupt handling, Cédric Le Goater, 2018/09/14
Re: [Qemu-devel] [PATCH 0/3] aspeed/i2c: fix receive done interrupt model, Peter Maydell, 2018/09/25