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[Qemu-devel] [PATCH v2 4/9] target/arm: Fix cortex-a7 id_isar0
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 4/9] target/arm: Fix cortex-a7 id_isar0 |
Date: |
Thu, 27 Sep 2018 14:13:17 -0700 |
The incorrect value advertised only thumb2 div without arm div.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 03bf28f533..020e79918b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1587,7 +1587,10 @@ static void cortex_a7_initfn(Object *obj)
cpu->id_mmfr1 = 0x40000000;
cpu->id_mmfr2 = 0x01240000;
cpu->id_mmfr3 = 0x02102211;
- cpu->id_isar0 = 0x01101110;
+ /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+ * table 4-41 gives 0x02101110, which includes the arm div insns.
+ */
+ cpu->id_isar0 = 0x02101110;
cpu->id_isar1 = 0x13112111;
cpu->id_isar2 = 0x21232041;
cpu->id_isar3 = 0x11112131;
--
2.17.1
- [Qemu-devel] [PATCH v2 7/9] target/arm: Convert t32ee from feature bit to isar3 test, (continued)
- [Qemu-devel] [PATCH v2 7/9] target/arm: Convert t32ee from feature bit to isar3 test, Richard Henderson, 2018/09/27
- [Qemu-devel] [PATCH v2 6/9] target/arm: Convert jazelle from feature bit to isar1 test, Richard Henderson, 2018/09/27
- [Qemu-devel] [PATCH v2 1/9] target/arm: Define fields of ISAR registers, Richard Henderson, 2018/09/27
- [Qemu-devel] [PATCH v2 9/9] target/arm: Convert v8.2-fp16 from feature bit to pfr0 test, Richard Henderson, 2018/09/27
- [Qemu-devel] [PATCH v2 8/9] target/arm: Convert sve from feature bit to pfr0 test, Richard Henderson, 2018/09/27
- [Qemu-devel] [PATCH v2 4/9] target/arm: Fix cortex-a7 id_isar0,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 5/9] target/arm: Convert division from feature bits to isar0 tests, Richard Henderson, 2018/09/27
- [Qemu-devel] [PATCH v2 3/9] target/arm: Align cortex-r5 id_isar0, Richard Henderson, 2018/09/27