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[Qemu-devel] [PULL 08/79] util: add atomic64
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 08/79] util: add atomic64 |
Date: |
Sun, 30 Sep 2018 10:12:06 +0200 |
From: "Emilio G. Cota" <address@hidden>
This introduces read/set accessors for int64_t and uint64_t.
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
include/qemu/atomic.h | 34 +++++++++++++++++++++
util/Makefile.objs | 1 +
util/atomic64.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++
util/cacheinfo.c | 3 ++
4 files changed, 121 insertions(+)
create mode 100644 util/atomic64.c
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index de3e36f..f6993a8 100644
--- a/include/qemu/atomic.h
+++ b/include/qemu/atomic.h
@@ -450,4 +450,38 @@
_oldn; \
})
+/* Abstractions to access atomically (i.e. "once") i64/u64 variables */
+#ifdef CONFIG_ATOMIC64
+static inline int64_t atomic_read_i64(const int64_t *ptr)
+{
+ /* use __nocheck because sizeof(void *) might be < sizeof(u64) */
+ return atomic_read__nocheck(ptr);
+}
+
+static inline uint64_t atomic_read_u64(const uint64_t *ptr)
+{
+ return atomic_read__nocheck(ptr);
+}
+
+static inline void atomic_set_i64(int64_t *ptr, int64_t val)
+{
+ atomic_set__nocheck(ptr, val);
+}
+
+static inline void atomic_set_u64(uint64_t *ptr, uint64_t val)
+{
+ atomic_set__nocheck(ptr, val);
+}
+
+static inline void atomic64_init(void)
+{
+}
+#else /* !CONFIG_ATOMIC64 */
+int64_t atomic_read_i64(const int64_t *ptr);
+uint64_t atomic_read_u64(const uint64_t *ptr);
+void atomic_set_i64(int64_t *ptr, int64_t val);
+void atomic_set_u64(uint64_t *ptr, uint64_t val);
+void atomic64_init(void);
+#endif /* !CONFIG_ATOMIC64 */
+
#endif /* QEMU_ATOMIC_H */
diff --git a/util/Makefile.objs b/util/Makefile.objs
index 0e88899..0820923 100644
--- a/util/Makefile.objs
+++ b/util/Makefile.objs
@@ -3,6 +3,7 @@ util-obj-y += bufferiszero.o
util-obj-y += lockcnt.o
util-obj-y += aiocb.o async.o aio-wait.o thread-pool.o qemu-timer.o
util-obj-y += main-loop.o iohandler.o
+util-obj-$(call lnot,$(CONFIG_ATOMIC64)) += atomic64.o
util-obj-$(CONFIG_POSIX) += aio-posix.o
util-obj-$(CONFIG_POSIX) += compatfd.o
util-obj-$(CONFIG_POSIX) += event_notifier-posix.o
diff --git a/util/atomic64.c b/util/atomic64.c
new file mode 100644
index 0000000..b198a6c
--- /dev/null
+++ b/util/atomic64.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2018, Emilio G. Cota <address@hidden>
+ *
+ * License: GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "qemu/atomic.h"
+#include "qemu/thread.h"
+
+#ifdef CONFIG_ATOMIC64
+#error This file must only be compiled if !CONFIG_ATOMIC64
+#endif
+
+/*
+ * When !CONFIG_ATOMIC64, we serialize both reads and writes with spinlocks.
+ * We use an array of spinlocks, with padding computed at run-time based on
+ * the host's dcache line size.
+ * We point to the array with a void * to simplify the padding's computation.
+ * Each spinlock is located every lock_size bytes.
+ */
+static void *lock_array;
+static size_t lock_size;
+
+/*
+ * Systems without CONFIG_ATOMIC64 are unlikely to have many cores, so we use a
+ * small array of locks.
+ */
+#define NR_LOCKS 16
+
+static QemuSpin *addr_to_lock(const void *addr)
+{
+ uintptr_t a = (uintptr_t)addr;
+ uintptr_t idx;
+
+ idx = a >> qemu_dcache_linesize_log;
+ idx ^= (idx >> 8) ^ (idx >> 16);
+ idx &= NR_LOCKS - 1;
+ return lock_array + idx * lock_size;
+}
+
+#define GEN_READ(name, type) \
+ type name(const type *ptr) \
+ { \
+ QemuSpin *lock = addr_to_lock(ptr); \
+ type ret; \
+ \
+ qemu_spin_lock(lock); \
+ ret = *ptr; \
+ qemu_spin_unlock(lock); \
+ return ret; \
+ }
+
+GEN_READ(atomic_read_i64, int64_t)
+GEN_READ(atomic_read_u64, uint64_t)
+#undef GEN_READ
+
+#define GEN_SET(name, type) \
+ void name(type *ptr, type val) \
+ { \
+ QemuSpin *lock = addr_to_lock(ptr); \
+ \
+ qemu_spin_lock(lock); \
+ *ptr = val; \
+ qemu_spin_unlock(lock); \
+ }
+
+GEN_SET(atomic_set_i64, int64_t)
+GEN_SET(atomic_set_u64, uint64_t)
+#undef GEN_SET
+
+void atomic64_init(void)
+{
+ int i;
+
+ lock_size = ROUND_UP(sizeof(QemuSpin), qemu_dcache_linesize);
+ lock_array = qemu_memalign(qemu_dcache_linesize, lock_size * NR_LOCKS);
+ for (i = 0; i < NR_LOCKS; i++) {
+ QemuSpin *lock = lock_array + i * lock_size;
+
+ qemu_spin_init(lock);
+ }
+}
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index 6c8fe79..3cd080b 100644
--- a/util/cacheinfo.c
+++ b/util/cacheinfo.c
@@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
+#include "qemu/atomic.h"
int qemu_icache_linesize = 0;
int qemu_icache_linesize_log;
@@ -182,4 +183,6 @@ static void __attribute__((constructor))
init_cache_info(void)
qemu_icache_linesize_log = ctz32(isize);
qemu_dcache_linesize = dsize;
qemu_dcache_linesize_log = ctz32(dsize);
+
+ atomic64_init();
}
--
1.8.3.1
- [Qemu-devel] [PULL 00/79] Misc QEMU patches for 2018-09-30, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 03/79] es1370: fix ADC_FRAMEADR and ADC_FRAMECNT, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 02/79] qsp: hide indirect function calls from Coverity, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 04/79] ps2: prevent changing irq state on save and load, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 06/79] cpus: initialize timers_state.vm_clock_lock, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 08/79] util: add atomic64,
Paolo Bonzini <=
- [Qemu-devel] [PULL 07/79] cacheinfo: add i/d cache_linesize_log, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 05/79] atomic: fix comment s/x64_64/x86_64/, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 01/79] virtio: Return true from virtio_queue_empty if broken, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 09/79] tests: add atomic64-bench, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 16/79] hostmem-memfd: add checks before adding hostmem-memfd & properties, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 13/79] cpus: access .qemu_icount with atomic64, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 12/79] cpus: take seqlock across qemu_icount updates, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 14/79] cpus: access .qemu_icount_bias with atomic64, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 17/79] kvm: x86: Fix kvm_arch_fixup_msi_route for remap-less case, Paolo Bonzini, 2018/09/30
- [Qemu-devel] [PULL 22/79] serial: fix DLL writes, Paolo Bonzini, 2018/09/30