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[Qemu-devel] [PULL 05/15] target/s390x: exception on non-aligned LPSW(E)
From: |
Cornelia Huck |
Subject: |
[Qemu-devel] [PULL 05/15] target/s390x: exception on non-aligned LPSW(E) |
Date: |
Thu, 4 Oct 2018 17:28:47 +0200 |
From: Pavel Zbitskiy <address@hidden>
Both LPSW and LPSWE should raise a specification exception when their
operand is not doubleword aligned.
Signed-off-by: Pavel Zbitskiy <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
---
target/s390x/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 7363aabf3a..59b1e5893c 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2835,7 +2835,8 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
+ MO_TEUL | MO_ALIGN_8);
tcg_gen_addi_i64(o->in2, o->in2, 4);
tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
/* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
@@ -2855,7 +2856,8 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps
*o)
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
+ MO_TEQ | MO_ALIGN_8);
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
gen_helper_load_psw(cpu_env, t1, t2);
--
2.14.4
- [Qemu-devel] [PULL 00/15] s390x updates, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 03/15] hw/s390x/ioinst: Fix alignment problem in struct SubchDev, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 01/15] hw/s390x/ipl: Fix alignment problems of S390IPLState members, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 05/15] target/s390x: exception on non-aligned LPSW(E),
Cornelia Huck <=
- [Qemu-devel] [PULL 02/15] hw/s390x/css: Remove QEMU_PACKED from struct SenseId, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 04/15] s390x: Fence huge pages prior to 3.1, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 06/15] s390x: move tcg_s390_program_interrupt() into TCG code and mark it noreturn, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 07/15] s390x/tcg: factor out and fix DATA exception injection, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 08/15] s390x/tcg: store in the TB flags if AFP is enabled, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 09/15] s390x/tcg: support flags for instructions, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 10/15] s390x/tcg: add instruction flags for floating point instructions, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 11/15] s390x/tcg: check for AFP-register, BFP and DFP data exceptions, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 12/15] s390x/tcg: handle privileged instructions via flags, Cornelia Huck, 2018/10/04
- [Qemu-devel] [PULL 14/15] s390x/tcg: refactor specification checking, Cornelia Huck, 2018/10/04