[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v5 23/28] target/mips: Implement emulation of nanoMI
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 23/28] target/mips: Implement emulation of nanoMIPS EVA instructions |
Date: |
Fri, 12 Oct 2018 18:39:31 +0200 |
From: Dimitrije Nikolic <address@hidden>
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.
Signed-off-by: Dimitrije Nikolic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9e4aae5..7ef8ef0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1992,6 +1992,35 @@ static inline void check_nms(DisasContext *ctx)
}
}
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
+ * Config2 TL, and Config5 L2C are unset.
+ */
+static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
+{
+ if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
+ !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
+ !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
+ !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
+ !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
+ !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))
+ {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 EVA bit is NOT set.
+ */
+static inline void check_eva(DisasContext *ctx)
+{
+ if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
@@ -20217,6 +20246,105 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
break;
}
break;
+ case NM_P_LS_E0:
+ switch (extract32(ctx->opcode, 11, 4)) {
+ case NM_LBE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_ld(ctx, OPC_LBE, rt, rs, s);
+ break;
+ case NM_SBE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_st(ctx, OPC_SBE, rt, rs, s);
+ break;
+ case NM_LBUE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_ld(ctx, OPC_LBUE, rt, rs, s);
+ break;
+ case NM_P_PREFE:
+ if (rt == 31) {
+ /* case NM_SYNCIE */
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->base.is_jmp = DISAS_STOP;
+ } else {
+ /* case NM_PREFE */
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ /* Treat as NOP. */
+ }
+ break;
+ case NM_LHE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_ld(ctx, OPC_LHE, rt, rs, s);
+ break;
+ case NM_SHE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_st(ctx, OPC_SHE, rt, rs, s);
+ break;
+ case NM_LHUE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_ld(ctx, OPC_LHUE, rt, rs, s);
+ break;
+ case NM_CACHEE:
+ check_nms_dl_il_sl_tl_l2c(ctx);
+ gen_cache_operation(ctx, rt, rs, s);
+ break;
+ case NM_LWE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_ld(ctx, OPC_LWE, rt, rs, s);
+ break;
+ case NM_SWE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_st(ctx, OPC_SWE, rt, rs, s);
+ break;
+ case NM_P_LLE:
+ switch (extract32(ctx->opcode, 2, 2)) {
+ case NM_LLE:
+ check_xnp(ctx);
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_ld(ctx, OPC_LLE, rt, rs, s);
+ break;
+ case NM_LLWPE:
+ check_xnp(ctx);
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P_SCE:
+ switch (extract32(ctx->opcode, 2, 2)) {
+ case NM_SCE:
+ check_xnp(ctx);
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_st_cond(ctx, OPC_SCE, rt, rs, s);
+ break;
+ case NM_SCWPE:
+ check_xnp(ctx);
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
+ gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ }
+ break;
case NM_P_LS_WM:
case NM_P_LS_UAWM:
check_nms(ctx);
--
2.7.4
- [Qemu-devel] [PATCH v5 16/28] target/mips: Add CP0 SAARI and SAAR registers, (continued)
- [Qemu-devel] [PATCH v5 16/28] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 15/28] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 18/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 14/28] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 26/28] target/mips: Add DEC feature to mips32r6-generic CPU, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 23/28] target/mips: Implement emulation of nanoMIPS EVA instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 27/28] target/mips: Add MSA ASE to MIPS64R2-generic CPU, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 25/28] hw/mips: Add Data Scratch Pad RAM, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 21/28] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 24/28] hw/mips: Update ITU to utilise SAARI/SAAR registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 28/28] target/mips: Add I6500 core configuration, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 19/28] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/12
- Re: [Qemu-devel] [PATCH v5 00/28] Misc MIPS fixes and improvements for October 2018, Aleksandar Markovic, 2018/10/16