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[Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA inst
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions |
Date: |
Wed, 17 Oct 2018 14:33:55 +0200 |
From: Dimitrije Nikolic <address@hidden>
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Dimitrije Nikolic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a63509a..95efbbe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17131,6 +17131,40 @@ enum {
NM_P_SC = 0x0b,
};
+/* P.LS.E0 instruction pool */
+enum {
+ NM_LBE = 0x00,
+ NM_SBE = 0x01,
+ NM_LBUE = 0x02,
+ NM_P_PREFE = 0x03,
+ NM_LHE = 0x04,
+ NM_SHE = 0x05,
+ NM_LHUE = 0x06,
+ NM_CACHEE = 0x07,
+ NM_LWE = 0x08,
+ NM_SWE = 0x09,
+ NM_P_LLE = 0x0a,
+ NM_P_SCE = 0x0b,
+};
+
+/* P.PREFE instruction pool */
+enum {
+ NM_SYNCIE = 0x00,
+ NM_PREFE = 0x01,
+};
+
+/* P.LLE instruction pool */
+enum {
+ NM_LLE = 0x00,
+ NM_LLWPE = 0x01,
+};
+
+/* P.SCE instruction pool */
+enum {
+ NM_SCE = 0x00,
+ NM_SCWPE = 0x01,
+};
+
/* P.LS.WM instruction pool */
enum {
NM_LWM = 0x00,
--
2.7.4
- [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE, (continued)
- [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 10/27] target/mips: Add assembler mnemonics list for MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 01/27] mailmap: Add an item for Yongbok Kim, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 07/27] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 16/27] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/17