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[Qemu-devel] [PULL v2 10/28] target/mips: Add basic description of MXU A
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 10/28] target/mips: Add basic description of MXU ASE |
Date: |
Thu, 18 Oct 2018 20:47:35 +0200 |
From: Aleksandar Markovic <address@hidden>
Add a comment that contains a basic description of MXU ASE.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..46655bb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1389,6 +1389,26 @@ enum {
OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
};
+
+/*
+ * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
+ * ============================================
+ *
+ * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
+ * instructions set. It is designed to fit the needs of signal, graphical and
+ * video processing applications. MXU instruction set is used in Xburst family
+ * of microprocessors by Ingenic.
+ *
+ * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
+ * the control register.
+ *
+ * Compiled after:
+ *
+ * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
+ * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
+ */
+
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.7.4
- [Qemu-devel] [PULL v2 15/28] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), (continued)
- [Qemu-devel] [PULL v2 15/28] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 17/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 07/28] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 22/28] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 21/28] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 19/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 24/28] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 27/28] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 14/28] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 10/28] target/mips: Add basic description of MXU ASE,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 12/28] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 23/28] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 18/28] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 28/28] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 26/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 25/28] target/mips: Implement hardware page table walker for MIPS32, Aleksandar Markovic, 2018/10/18
- Re: [Qemu-devel] [PULL v2 00/28] MIPS queue October 2018, part 1, v2, Peter Maydell, 2018/10/19