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Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-ope


From: Aleksandar Markovic
Subject: Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU
Date: Fri, 19 Oct 2018 18:09:22 +0000

> Perhaps a better alternative is to define the MMI registers as 128-bit, 
> similar to
>
> static TCGv_u128 mmi_gpr[32];
>
> and then copy cpu_gpr to/from mmi_gpr as needed when running the MMIs?

Fredrik, hi.

I think this is fine. In any case, this could be changed, if we hit any 
obstacle related to this format later on during development.

But you don't have to spend much time on this right now. The definition of MMI 
registers is more 'nice-to-have' than a 'must'.

Regards,
Aleksandar


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