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Re: [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RV
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree |
Date: |
Tue, 23 Oct 2018 09:35:22 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -23,8 +23,7 @@ static bool trans_c_addi4spn(DisasContext *ctx,
> arg_c_addi4spn *a,
> {
> if (a->nzuimm == 0) {
> /* Reserved in ISA */
> - gen_exception_illegal(ctx);
> - return true;
> + return false;
Ah, the change for patch 16 got squished to the wrong patch.
> +static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a, uint16_t insn)
> +{
> + int shamt = a->shamt;
> + if (shamt == 0) {
> + /* For RV128 a shamt of 0 means a shift by 64 */
> + shamt = 64;
> + }
> + /* Ensure, that shamt[5] is zero for RV32 */
> + if (shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> + return trans_srli(ctx, &arg, insn);
> +}
> +
> +static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a, uint16_t insn)
> +{
> + if (a->shamt == 0) {
> + /* Reserved in ISA */
> + return false;
> + }
> +#ifdef TARGET_RISCV32
> + /* Ensure, that shamt[5] is zero for RV32 */
> + if (a->shamt >= 32) {
> + return false;
> + }
> +#endif
Same change as srli. Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence insns to decodetree, (continued)
- [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20
- Re: [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/20