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[Qemu-devel] [PATCH v7 02/20] target/mips: Define a bit for MXU in insn_
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v7 02/20] target/mips: Define a bit for MXU in insn_flags |
Date: |
Wed, 24 Oct 2018 14:18:29 +0200 |
From: Craig Janeczek <address@hidden>
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/mips-defs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 5177618..dbdb4b2 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -69,6 +69,7 @@
* bits 56-63: vendor-specific ASEs
*/
#define ASE_MMI 0x0100000000000000ULL
+#define ASE_MXU 0x0200000000000000ULL
/* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1)
--
2.7.4
[Qemu-devel] [PATCH v7 05/20] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/24