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[Qemu-devel] [PATCH v8 11/20] target/mips: Add emulation of non-MXU MULL
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v8 11/20] target/mips: Add emulation of non-MXU MULL within MXU decoding engine |
Date: |
Mon, 29 Oct 2018 12:25:19 +0100 |
From: Craig Janeczek <address@hidden>
Add emulation of non-MXU MULL within MXU decoding engine.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 13e158a..a98de28 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1648,7 +1648,7 @@ enum {
enum {
OPC_MXU_S32MADD = 0x00,
OPC_MXU_S32MADDU = 0x01,
- /* not assigned 0x02 */
+ OPC__MXU_MUL = 0x02,
OPC_MXU__POOL00 = 0x03,
OPC_MXU_S32MSUB = 0x04,
OPC_MXU_S32MSUBU = 0x05,
@@ -24907,6 +24907,11 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env,
DisasContext *ctx)
*/
static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
{
+ /*
+ * TODO: Investigate necessity of including handling of
+ * CLZ, CLO, SDBB in this function, as they belong to
+ * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
+ */
uint32_t opcode = extract32(ctx->opcode, 0, 6);
switch (opcode) {
@@ -24920,6 +24925,18 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI);
break;
+ case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
+ {
+ uint32_t rs, rt, rd, op1;
+
+ rs = extract32(ctx->opcode, 21, 5);
+ rt = extract32(ctx->opcode, 16, 5);
+ rd = extract32(ctx->opcode, 11, 5);
+ op1 = MASK_SPECIAL2(ctx->opcode);
+
+ gen_arith(ctx, op1, rd, rs, rt);
+ }
+ break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
break;
--
2.7.4
- [Qemu-devel] [PATCH v8 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', (continued)
- [Qemu-devel] [PATCH v8 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 08/20] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 09/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 10/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 15/20] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 16/20] target/mips: Add emulation of MXU instruction D16MAC, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 17/20] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 14/20] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 11/20] target/mips: Add emulation of non-MXU MULL within MXU decoding engine,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v8 20/20] target/mips: Amend MXU ASE overview note, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 18/20] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PATCH v8 19/20] target/mips: Move MXU_EN check one level higher, Aleksandar Markovic, 2018/10/29
- Re: [Qemu-devel] [PATCH v8 00/20] target/mips: Add limited support for Ingenic's MXU ASE, Aleksandar Markovic, 2018/10/29