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[Qemu-devel] [PATCH v7 10/12] target/arm: PMU: Set PMCR.N to 4
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v7 10/12] target/arm: PMU: Set PMCR.N to 4 |
Date: |
Mon, 5 Nov 2018 18:52:01 +0000 |
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.
Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e3ec36490c..11eb62bdda 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1753,7 +1753,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_W, .type = ARM_CP_NOP },
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
- * follow (although we don't actually implement any counters)
+ * follow.
*
* Performance registers fall into three categories:
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
@@ -5508,10 +5508,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement only the cycle
- * count register.
+ * field as main ID register, and we implement four counters in
+ * addition to the cycle count register.
*/
- unsigned int i, pmcrn = 0;
+ unsigned int i, pmcrn = 4;
ARMCPRegInfo pmcr = {
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 =
0,
.access = PL0_RW,
@@ -5526,7 +5526,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->midr & 0xff000000,
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
--
2.19.1
- Re: [Qemu-devel] [PATCH v7 03/12] target/arm: Swap PMU values before/after migrations, (continued)
- [Qemu-devel] [PATCH v7 02/12] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/11/05
- [Qemu-devel] [PATCH v7 06/12] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/11/05
- [Qemu-devel] [PATCH v7 08/12] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/11/05
- [Qemu-devel] [PATCH v7 07/12] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/11/05
- [Qemu-devel] [PATCH v7 09/12] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/11/05
- [Qemu-devel] [PATCH v7 10/12] target/arm: PMU: Set PMCR.N to 4,
Aaron Lindsay <=
- [Qemu-devel] [PATCH v7 11/12] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/11/05
- [Qemu-devel] [PATCH v7 12/12] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/11/05
- Re: [Qemu-devel] [PATCH v7 00/12] More fully implement ARM PMUv3, no-reply, 2018/11/06