Re: [Qemu-devel] [PATCH 0/4] target/arm: Minimize TLB flushing for ASID changes

[Peter Maydell]

On 29 October 2018 at 15:53, Richard Henderson
<address@hidden> wrote:
> In http://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg04181.html
> (already upstream) I added a check for ASID changes without realizing
> that TTBCR_EL1 has the A1 bit, controlling which register actually
> contains the active ASID.
>
> In http://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg04182.html
> I suggested a set of mmu_idx to flush when the ASID does change.  In
> follow-up, Peter suggested more.
>
> I now choose secure vs non-secure mmu_idx based on which register is being
> modified, not the current state of the cpu.  Unless I am mistaken, secure
> state can write to the non-secure registers.  Which means that the current
> state of the cpu is irrelevant and only the register matters.
>
> Peter suggested flushing S1E3 when changing ttbr0_s.  I can see how this
> is overlapped onto the EL3 (Secure Monitor) state, but I cannot see how
> the ASID is used from EL3.  The best evidence I can find for this is that
> there is no TLBIASID* register that is applicable to flushing EL3; that's
> not conclusive proof though.  So while I'm not sure it's necessary, I'm
> also not sure it isn't necessary, and so I've included S1E3 in the flush.

"TLBIASID" flushes EL3, when EL3 is AArch32 and you are in Secure PL1
(ie EL3). From the register spec:
"If executed in Secure state when EL3 is using AArch32, the Secure PL1&0
translation regime."
The spec's "SecurePL1&0 translation regime" is in QEMU ARMMMUIdx_S1E3.
TTBR0(S) contains an ASID if TTBCR(S).EAE is 1.

(If EL3 is AArch64 then there's no TTBR0(S), only TTBR_EL3, which doesn't
have an ASID.)

thanks
-- PMM