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[Qemu-devel] [PATCH v8 00/13] More fully implement ARM PMUv3
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v8 00/13] More fully implement ARM PMUv3 |
Date: |
Tue, 20 Nov 2018 21:26:26 +0000 |
The ARM PMU implementation currently contains a basic cycle counter, but
it is often useful to gather counts of other events, filter them based
on execution mode, and/or be notified on counter overflow. These patches
flesh out the implementations of various PMU registers including
PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent
arbitrary counter types, implement mode filtering, send interrupts on
counter overflow, and add instruction, cycle, and software increment
events.
Since v7 [1] I have made the following changes:
* Updated pmu_op_start/finish to not be called upon migration under KVM
* Added a patch updating PMCEID* to be 64-bit registers for AArch64 and
added PMCEID2/3 for AArch32
* Changed get_pmceid() return two full 64-bit register values (since the
underlying registers are now 64-bit post-ARMv8.1)
* Updated the comment for pmu_op_start/finish to match the
implementation
* Added a check so the pmu_timer is not freed if it was not originally
allocated
[1] - https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg00837.html
Aaron Lindsay (13):
migration: Add post_save function to VMStateDescription
target/arm: Reorganize PMCCNTR accesses
target/arm: Swap PMU values before/after migrations
target/arm: Filter cycle counter based on PMCCFILTR_EL0
target/arm: Allow AArch32 access for PMCCFILTR
target/arm: Implement PMOVSSET
target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
target/arm: Add array for supported PMU events, generate
PMCEID[01]_EL0
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
target/arm: PMU: Add instruction and cycle events
target/arm: PMU: Set PMCR.N to 4
target/arm: Implement PMSWINC
target/arm: Send interrupts on PMU counter overflow
docs/devel/migration.rst | 9 +-
include/migration/vmstate.h | 1 +
migration/vmstate.c | 13 +-
target/arm/cpu.c | 28 +-
target/arm/cpu.h | 71 +++-
target/arm/cpu64.c | 4 -
target/arm/helper.c | 801 ++++++++++++++++++++++++++++++++----
target/arm/machine.c | 24 ++
8 files changed, 846 insertions(+), 105 deletions(-)
--
2.19.1
- [Qemu-devel] [PATCH v8 00/13] More fully implement ARM PMUv3,
Aaron Lindsay <=
- [Qemu-devel] [PATCH v8 01/13] migration: Add post_save function to VMStateDescription, Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 03/13] target/arm: Swap PMU values before/after migrations, Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 02/13] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 04/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23], Aaron Lindsay, 2018/11/20
- [Qemu-devel] [PATCH v8 11/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/11/20