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Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the numb
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts |
Date: |
Wed, 21 Nov 2018 10:17:34 -0800 |
On Wed, Nov 21, 2018 at 9:58 AM Logan Gunthorpe <address@hidden> wrote:
>
>
>
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Increase the number of interrupts to match the HiFive Unleashed board.
> >
> > Signed-off-by: Alistair Francis <address@hidden>
> > ---
> > include/hw/riscv/virt.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> > index 91163d6cbf..7cb2742070 100644
> > --- a/include/hw/riscv/virt.h
> > +++ b/include/hw/riscv/virt.h
> > @@ -45,7 +45,7 @@ enum {
> > UART0_IRQ = 10,
> > VIRTIO_IRQ = 1, /* 1 to 8 */
> > VIRTIO_COUNT = 8,
> > - VIRTIO_NDEV = 10
> > + VIRTIO_NDEV = 0x35
>
> Why 0x35? Based on the PCI patch we are using only 36 interrupts, not 53...
This is just for future proofing. There is no reason to set the number
lower then the number of interrupts we have, now hopefully this won't
keep churning every time we add a device.
Alistair
>
> Logan
- [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/11/21
- [Qemu-devel] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/11/21
- [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/11/21
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts,
Alistair Francis <=
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/11/21
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/11/21
- Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
[Qemu-devel] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/11/21
[Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21