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[Qemu-devel] Question about piix3's PIRQC register set

From: Li Qiang
Subject: [Qemu-devel] Question about piix3's PIRQC register set
Date: Wed, 5 Dec 2018 23:13:07 +0800

Hello Paolo Alex, and all,

I have a question when reading the ‘vfio_intx_enable’ function.

There calls ‘pci_device_route_intx_to_irq’ to get the ‘irq number’ from 
a device intx info.

It is read from ‘piix3->dev.config[PIIX_PIRQC + pin];’ in 

Here my question when the piix3’s PIRQx route control registers is set and by 
I mean when this ‘‘piix3->dev.config[PIIX_PIRQC + pin];’’ is set?

Once I think this is set by seabios. 
But seems it is not as this function is called in vfio_realize, the guest 
dones’t begin.

Li Qiang 

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