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Re: [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
Date: Wed, 5 Dec 2018 15:00:43 +0000

On Wed, 5 Dec 2018 at 13:00, Aaron Lindsay <address@hidden> wrote:
> On Dec 03 16:57, Richard Henderson wrote:
> > Yes.  It would appear that this feature should be controlled by
> > ID_DFR0.PerfMon.  So,
> >
> >   if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4)
> >
> > once the appropriate FIELDs are added to cpu.h.
> >
> > Since this test is not used within translate*.c, there is no need to move
> > id_dfr* into ARMISARegisters.  Since these are only aliases, they do not 
> > affect
> > migration, and so do not (yet) need to be filled in by kvm.
> Sounds reasonable to me. One clarification - do we also need to guard
> against the 0b1111 value for ID_DFR0.PerfMon, which implies an
> implementation-defined, non-PMUv3 PMU, or is it safe to assume no one
> will attempt that flavor in QEMU?

We should check for 0xf, yes, following the recommended check
logic described in the Arm ARM section "Alternative ID scheme used
for the Performance Monitors Extension version". It doesn't
seem likely that we'll end up with the 0xf case but we might
as well avoid the question in advance...

-- PMM

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