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[Qemu-devel] [PATCH 09/34] target/arm: Use vector minmax expanders for a
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/34] target/arm: Use vector minmax expanders for aarch64 |
Date: |
Mon, 17 Dec 2018 22:38:46 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 35 ++++++++++++++---------------------
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2d6f8c1b4f..bef21ada71 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10452,6 +10452,20 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
}
switch (opcode) {
+ case 0x0c: /* SMAX, UMAX */
+ if (u) {
+ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
+ } else {
+ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size);
+ }
+ return;
+ case 0x0d: /* SMIN, UMIN */
+ if (u) {
+ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size);
+ } else {
+ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size);
+ }
+ return;
case 0x10: /* ADD, SUB */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size);
@@ -10613,27 +10627,6 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genenvfn = fns[size][u];
break;
}
- case 0xc: /* SMAX, UMAX */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_max_s8, gen_helper_neon_max_u8 },
- { gen_helper_neon_max_s16, gen_helper_neon_max_u16 },
- { tcg_gen_smax_i32, tcg_gen_umax_i32 },
- };
- genfn = fns[size][u];
- break;
- }
-
- case 0xd: /* SMIN, UMIN */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
- { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
- { tcg_gen_smin_i32, tcg_gen_umin_i32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0xe: /* SABD, UABD */
case 0xf: /* SABA, UABA */
{
--
2.17.2
- [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 04/34] tcg: Add write_aofs to GVecGen4, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 09/34] target/arm: Use vector minmax expanders for aarch64,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/34] tcg/i386: Implement vector minmax arithmetic, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 03/34] tcg: Add gvec expanders for nand, nor, eqv, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 15/34] target/ppc: merge ppc_vsr_t and ppc_avr_t union types, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 28/34] target/ppc: Remove vscr_nj and vscr_sat, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 06/34] tcg/i386: Implement vector saturating arithmetic, Richard Henderson, 2018/12/18