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[Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions |
Date: |
Wed, 26 Dec 2018 07:54:59 +1100 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 01b4443d6d..48399480b2 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -596,3 +596,37 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
}
+
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+ tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
+}
--
2.17.2
- [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit, (continued)
- [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions,
Richard Henderson <=
- [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 22/42] disas: Add RISC-V support, Richard Henderson, 2018/12/25