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[Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hin
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space |
Date: |
Wed, 9 Jan 2019 08:31:04 +1000 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v3: Use binary literals.
---
target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++-----
1 file changed, 81 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 37a57af715..b72aea3e97 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t insn,
}
switch (selector) {
- case 0: /* NOP */
- return;
- case 3: /* WFI */
+ case 0b00000: /* NOP */
+ break;
+ case 0b00011: /* WFI */
s->base.is_jmp = DISAS_WFI;
- return;
+ break;
+ case 0b00001: /* YIELD */
/* When running in MTTCG we don't generate jumps to the yield and
* WFE helpers as it won't affect the scheduling of other vCPUs.
* If we wanted to more completely model WFE/SEV so we don't busy
* spin unnecessarily we would need to do something more involved.
*/
- case 1: /* YIELD */
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
s->base.is_jmp = DISAS_YIELD;
}
- return;
- case 2: /* WFE */
+ break;
+ case 0b00010: /* WFE */
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
s->base.is_jmp = DISAS_WFE;
}
- return;
- case 4: /* SEV */
- case 5: /* SEVL */
+ break;
+ case 0b00100: /* SEV */
+ case 0b00101: /* SEVL */
/* we treat all as NOP at least for now */
- return;
+ break;
+ case 0b00111: /* XPACLRI */
+ if (s->pauth_active) {
+ gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
+ }
+ break;
+ case 0b01000: /* PACIA1716 */
+ if (s->pauth_active) {
+ gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ }
+ break;
+ case 0b01010: /* PACIB1716 */
+ if (s->pauth_active) {
+ gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ }
+ break;
+ case 0b01100: /* AUTIA1716 */
+ if (s->pauth_active) {
+ gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ }
+ break;
+ case 0b01110: /* AUTIB1716 */
+ if (s->pauth_active) {
+ gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ }
+ break;
+ case 0b11000: /* PACIAZ */
+ if (s->pauth_active) {
+ gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
+ new_tmp_a64_zero(s));
+ }
+ break;
+ case 0b11001: /* PACIASP */
+ if (s->pauth_active) {
+ gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ }
+ break;
+ case 0b11010: /* PACIBZ */
+ if (s->pauth_active) {
+ gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30],
+ new_tmp_a64_zero(s));
+ }
+ break;
+ case 0b11011: /* PACIBSP */
+ if (s->pauth_active) {
+ gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ }
+ break;
+ case 0b11100: /* AUTIAZ */
+ if (s->pauth_active) {
+ gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30],
+ new_tmp_a64_zero(s));
+ }
+ break;
+ case 0b11101: /* AUTIASP */
+ if (s->pauth_active) {
+ gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ }
+ break;
+ case 0b11110: /* AUTIBZ */
+ if (s->pauth_active) {
+ gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30],
+ new_tmp_a64_zero(s));
+ }
+ break;
+ case 0b11111: /* AUTIBSP */
+ if (s->pauth_active) {
+ gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ }
+ break;
default:
/* default specified as NOP equivalent */
- return;
+ break;
}
}
--
2.17.2
- [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 01/31] target/arm: Add state for the ARMv8.3-PAuth extension, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 02/31] target/arm: Add SCTLR bits through ARMv8.5, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 03/31] target/arm: Add PAuth active bit to tbflags, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 05/31] target/arm: Add PAuth helpers, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 07/31] target/arm: Rearrange decode in disas_data_proc_1src, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 08/31] target/arm: Decode PAuth within disas_data_proc_1src, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 09/31] target/arm: Decode PAuth within disas_data_proc_2src, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 11/31] target/arm: Add new_pc argument to helper_exception_return, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 10/31] target/arm: Move helper_exception_return to helper-a64.c, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 12/31] target/arm: Rearrange decode in disas_uncond_b_reg, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 13/31] target/arm: Decode PAuth within disas_uncond_b_reg, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx, Richard Henderson, 2019/01/08
- [Qemu-devel] [PATCH v3 14/31] target/arm: Decode Load/store register (pac), Richard Henderson, 2019/01/08