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Re: [Qemu-devel] [PATCH v2 09/12] tests/tcg/mips: Test R5900 three-opera

From: Fredrik Noring
Subject: Re: [Qemu-devel] [PATCH v2 09/12] tests/tcg/mips: Test R5900 three-operand MADDU1
Date: Sun, 13 Jan 2019 19:57:08 +0100
User-agent: Mutt/1.10.1 (2018-07-13)

Hi Aleksandar,

> - Suggestion: The next MIPS pull request is scehuled for Friday,
> Jan 18, 2018. It would be fantastic if you could prepare the
> following by Jan 14:
>   * Add 32 TCGv_i64 registers that would represent higher halves
>   of R5900 general purpose registers.


>   * Add TCGv_i32 register SA (shift amount).

See notes below.

>   * Perhaps consider adding higher halves of registers HI an LO
>   independently on HI/LO array used by DSP.

For HI1 and LO1 only? I'm asking since HI0 and LO0 are implemented with
the DSP array anyway, for all ISAs.

>   * It is customary to implement R/W access while introducing
>   such registers:
>     * Implement R/W access instructions to higher halves of
>     R5900 GPRs:
>       * LQ

Done, including PCPYUD and PCPYLD for proper testing!

>       * SQ

Done, including testing!

>     * Implement R/W access instructions to SA register:
>       * MFSA

The TX79 manual says that "the sole purpose of this instruction is to
permit the shift amount to be saved during a context switch" and that
"the shift amount is encoded in SA in an implementation-defined manner"
so it seems to make more sense for system mode rather than user mode?

One may want to choose an implementation that matches the actual R5900
hardware, even though the manual says it's arbitrary.

>       * MTSA


>       * MTSAH
>       * MTSAB

These instructions do not appear to be usable unless the corresponding
shift instructions are implemented as well?

I will post an R5900 multimedia instruction patch series shortly.


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