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[Qemu-devel] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty |
Date: |
Mon, 14 Jan 2019 23:57:59 +0000 |
From: Richard Henderson <address@hidden>
Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html
Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Co-authored-by: Richard Henderson <address@hidden>
Co-authored-by: Michael Clark <address@hidden>
---
target/riscv/csr.c | 12 ------------
target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e7e7d16b8..5714147689 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -317,18 +317,6 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
- /* Note: this is a workaround for an issue where mstatus.FS
- does not report dirty after floating point operations
- that modify floating point state. This workaround is
- technically compliant with the RISC-V Privileged
- specification as it is legal to return only off, or dirty.
- at the expense of extra floating point save/restore. */
-
- /* FP is always dirty or off */
- if (mstatus & MSTATUS_FS) {
- mstatus |= MSTATUS_FS;
- }
-
int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3d07d651b6..0581b3c1f7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,6 +651,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int
rs1, int rs2,
tcg_temp_free(dat);
}
+#ifndef CONFIG_USER_ONLY
+/* The states of mstatus_fs are:
+ * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+ * We will have already diagnosed disabled state,
+ * and need to turn initial/clean into dirty.
+ */
+static void mark_fs_dirty(DisasContext *ctx)
+{
+ TCGv tmp;
+ if (ctx->mstatus_fs == MSTATUS_FS) {
+ return;
+ }
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_fs = MSTATUS_FS;
+
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_temp_free(tmp);
+}
+#else
+static inline void mark_fs_dirty(DisasContext *ctx) { }
+#endif
+
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
@@ -679,6 +704,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc,
int rd,
break;
}
tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
}
static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
@@ -944,6 +971,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
int rs1, int rs2, int rm)
{
TCGv t0 = NULL;
+ bool fp_output = true;
if (ctx->mstatus_fs == 0) {
goto do_illegal;
@@ -1006,6 +1034,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_W_S:
@@ -1035,6 +1064,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_S_W:
@@ -1085,6 +1115,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FMV_S_X:
@@ -1177,6 +1208,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_W_D:
@@ -1206,6 +1238,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_D_W:
@@ -1254,6 +1287,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
default:
goto do_illegal;
}
+ fp_output = false;
break;
#if defined(TARGET_RISCV64)
@@ -1271,7 +1305,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t
opc, int rd,
tcg_temp_free(t0);
}
gen_exception_illegal(ctx);
- break;
+ return;
+ }
+
+ if (fp_output) {
+ mark_fs_dirty(ctx);
}
}
--
2.19.1
[Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers, Alistair Francis, 2019/01/14