Re: [Qemu-devel] [PATCH 5/9] target/mips: Support the R5900 LQ multimedia instruction

[Aleksandar Markovic]

> From: Fredrik Noring <address@hidden>
> Sent: Sunday, January 13, 2019 8:05 PM
> To: Aleksandar Markovic; Aurelien Jarno; Philippe Mathieu-Daudé
> Cc: Jürgen Urban; Maciej W. Rozycki; address@hidden
> Subject: [PATCH 5/9] target/mips: Support the R5900 LQ multimedia instruction
> 
> Signed-off-by: Fredrik Noring <address@hidden>

Please provide a commit message, even if it is the same as the patch title.

> ---
>  target/mips/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 8c350729bc..79505bb6c2 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -2626,6 +2626,17 @@ static inline void gen_store_gpr (TCGv t, int reg)
>          tcg_gen_mov_tl(cpu_gpr[reg], t);
>  }
> 
> +#if defined(TARGET_MIPS64)
> +/* 128-bit multimedia register moves. */
> +static inline void gen_store_mmr(TCGv_i64 hi, TCGv_i64 lo, int reg)
> +{
> +    if (reg != 0) {
> +        tcg_gen_mov_i64(cpu_mmr[reg], hi);
> +        tcg_gen_mov_i64(cpu_gpr[reg], lo);
> +    }
> +}
> +#endif /* defined(TARGET_MIPS64) */
> +
>  /* Moves to/from shadow registers. */
>  static inline void gen_load_srsgpr (int from, int to)
>  {
> @@ -27463,7 +27474,40 @@ static void decode_mmi(CPUMIPSState *env, 
> DisasContext *ctx)
> 
>  static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
>  {
> -    generate_exception_end(ctx, EXCP_RI);    /* TODO: MMI_OPC_LQ */
> +#if !defined(TARGET_MIPS64)
> +    generate_exception_end(ctx, EXCP_RI);
> +#else

TARGET_MIPS64 should always be defined for R5900, IMHO.

> +    int base = extract32(ctx->opcode, 21, 5);
> +    int rt = extract32(ctx->opcode, 16, 5);
> +    int offset = sextract32(ctx->opcode, 0, 16);
> +
> +    TCGv_i64 addr = tcg_temp_new_i64();
> +    TCGv_i64 val0 = tcg_temp_new_i64();
> +    TCGv_i64 val1 = tcg_temp_new_i64();
> +
> +    gen_base_offset_addr(ctx, addr, base, offset);
> +
> +    /*
> +     * The least significant four bits of the effective address are
> +     * masked to zero, effectively creating an aligned address. No
> +     * address exceptions due to alignment are possible.
> +     */
> +    tcg_gen_andi_i64(addr, addr, ~0xFULL);
> +
> +    tcg_gen_qemu_ld_i64(val0, addr, ctx->mem_idx, MO_UNALN | MO_64);
> +    tcg_gen_addi_i64(addr, addr, 8);
> +    tcg_gen_qemu_ld_i64(val1, addr, ctx->mem_idx, MO_UNALN | MO_64);
> +
> +#if defined(TARGET_WORDS_BIGENDIAN)
> +    gen_store_mmr(val0, val1, rt);
> +#else
> +    gen_store_mmr(val1, val0, rt);
> +#endif
> +
> +    tcg_temp_free_i64(val1);
> +    tcg_temp_free_i64(val0);
> +    tcg_temp_free_i64(addr);
> +#endif /* defined(TARGET_MIPS64) */
>  }
> 
>  static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
> --
> 2.19.2