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[Qemu-devel] [PATCH 1/3] target/mips: Add preprocessor constants for CP0
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH 1/3] target/mips: Add preprocessor constants for CP0 subregisters |
Date: |
Wed, 16 Jan 2019 14:05:47 +0100 |
From: Aleksandar Markovic <address@hidden>
Add preprocessor constants for CP0 subregisters. The names of
the subregisters were chosen to be in sync with the table of
corresponding assembler mnemonics found in the documentation
for I6500 and I6400 (release 1.0).
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 114 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 114 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 48e86d1..294aef0 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -267,6 +267,120 @@ typedef struct mips_def_t mips_def_t;
#define CPO_REGISTER_31 31
+/* CP0 Register 00 */
+#define CPO_REG00__INDEX 0
+#define CPO_REG00__VPCONTROL 4
+/* CP0 Register 01 */
+/* CP0 Register 02 */
+#define CPO_REG02__ENTRYLO0 0
+/* CP0 Register 03 */
+#define CPO_REG03__ENTRYLO1 0
+#define CPO_REG03__GLOBALNUM 1
+/* CP0 Register 04 */
+#define CPO_REG04__CONTEXT 0
+#define CPO_REG04__USERLOCAL 2
+#define CPO_REG04__DBGCONTEXTID 4
+#define CPO_REG00__MMID 5
+/* CP0 Register 05 */
+#define CPO_REG05__PAGEMASK 0
+#define CPO_REG05__PAGEGRAIN 1
+/* CP0 Register 06 */
+#define CPO_REG06__WIRED 0
+/* CP0 Register 07 */
+#define CPO_REG07__HWRENA 0
+/* CP0 Register 08 */
+#define CPO_REG08__BADVADDR 0
+#define CPO_REG08__BADINSTR 1
+#define CPO_REG08__BADINSTRP 2
+/* CP0 Register 09 */
+#define CPO_REG09__COUNT 0
+#define CPO_REG09__SAARI 6
+#define CPO_REG09__SAAR 7
+/* CP0 Register 10 */
+#define CPO_REG10__ENTRYHI 0
+#define CPO_REG10__GUESTCTL1 4
+#define CPO_REG10__GUESTCTL2 5
+/* CP0 Register 11 */
+#define CPO_REG11__COMPARE 0
+#define CPO_REG11__GUESTCTL0EXT 4
+/* CP0 Register 12 */
+#define CPO_REG12__STATUS 0
+#define CPO_REG12__INTCTL 1
+#define CPO_REG12__SRSCTL 2
+#define CPO_REG12__GUESTCTL0 6
+#define CPO_REG12__GTOFFSET 7
+/* CP0 Register 13 */
+#define CPO_REG13__CAUSE 0
+/* CP0 Register 14 */
+#define CPO_REG14__EPC 0
+/* CP0 Register 15 */
+#define CPO_REG15__PRID 0
+#define CPO_REG15__EBASE 1
+#define CPO_REG15__CDMMBASE 2
+#define CPO_REG15__CMGCRBASE 3
+/* CP0 Register 16 */
+#define CPO_REG16__CONFIG 0
+#define CPO_REG16__CONFIG1 1
+#define CPO_REG16__CONFIG2 2
+#define CPO_REG16__CONFIG3 3
+#define CPO_REG16__CONFIG4 4
+#define CPO_REG16__CONFIG5 5
+#define CPO_REG00__CONFIG7 7
+/* CP0 Register 17 */
+#define CPO_REG17__LLADDR 0
+#define CPO_REG17__MAAR 1
+#define CPO_REG17__MAARI 2
+/* CP0 Register 18 */
+#define CPO_REG18__WATCHLO0 0
+#define CPO_REG18__WATCHLO1 1
+#define CPO_REG18__WATCHLO2 2
+#define CPO_REG18__WATCHLO3 3
+/* CP0 Register 19 */
+#define CPO_REG19__WATCHHI0 0
+#define CPO_REG19__WATCHHI1 1
+#define CPO_REG19__WATCHHI2 2
+#define CPO_REG19__WATCHHI3 3
+/* CP0 Register 20 */
+#define CPO_REG20__XCONTEXT 0
+/* CP0 Register 21 */
+/* CP0 Register 22 */
+/* CP0 Register 23 */
+#define CPO_REG23__DEBUG 0
+/* CP0 Register 24 */
+#define CPO_REG24__DEPC 0
+/* CP0 Register 25 */
+#define CPO_REG25__PERFCTL0 0
+#define CPO_REG25__PERFCNT0 1
+#define CPO_REG25__PERFCTL1 2
+#define CPO_REG25__PERFCNT1 3
+#define CPO_REG25__PERFCTL2 4
+#define CPO_REG25__PERFCNT2 5
+#define CPO_REG25__PERFCTL3 6
+#define CPO_REG25__PERFCNT3 7
+/* CP0 Register 26 */
+#define CPO_REG00__ERRCTL 0
+/* CP0 Register 27 */
+#define CPO_REG27__CACHERR 0
+/* CP0 Register 28 */
+#define CPO_REG28__ITAGLO 0
+#define CPO_REG28__IDATALO 1
+#define CPO_REG28__DTAGLO 2
+#define CPO_REG28__DDATALO 3
+/* CP0 Register 29 */
+#define CPO_REG29__IDATAHI 1
+#define CPO_REG29__DDATAHI 3
+/* CP0 Register 30 */
+#define CPO_REG30__ERROREPC 0
+/* CP0 Register 31 */
+#define CPO_REG31__DESAVE 0
+#define CPO_REG31__KSCRATCH1 2
+#define CPO_REG31__KSCRATCH2 3
+#define CPO_REG31__KSCRATCH3 4
+#define CPO_REG31__KSCRATCH4 5
+#define CPO_REG31__KSCRATCH5 6
+#define CPO_REG31__KSCRATCH6 7
+
+
typedef struct TCState TCState;
struct TCState {
target_ulong gpr[32];
--
2.7.4