Re: [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter

[Greg Kurz]

On Thu, 17 Jan 2019 08:53:24 +0100
Cédric Le Goater <address@hidden> wrote:

> It provides a mean to retrieve the XiveTCTX of a CPU. This will become
> necessary with future changes which move the interrupt presenter
> object pointers under the PowerPCCPU machine_data.
> 
> The PowerNV machine has an extra requirement on TIMA accesses that
> this new method addresses. The machine can perform indirect loads and
> stores on the TIMA on behalf of another CPU. The PIR being defined in
> the controller registers, we need a way to peek in the controller
> model to find the PIR value.
> 
> The XiveTCTX is moved above the XiveRouter definition to avoid forward
> typedef declarations.
> 
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---

Reviewed-by: Greg Kurz <address@hidden>

>  include/hw/ppc/xive.h | 57 ++++++++++++++++++++++---------------------
>  hw/intc/spapr_xive.c  |  8 ++++++
>  hw/intc/xive.c        | 16 +++++++-----
>  3 files changed, 47 insertions(+), 34 deletions(-)
> 
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index 5d31c801ee53..ec3bb2aae45a 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsrc, 
> uint32_t srcno,
>  
>  void xive_source_set_irq(void *opaque, int srcno, int val);
>  
> +/*
> + * XIVE Thread interrupt Management (TM) context
> + */
> +
> +#define TYPE_XIVE_TCTX "xive-tctx"
> +#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
> +
> +/*
> + * XIVE Thread interrupt Management register rings :
> + *
> + *   QW-0  User       event-based exception state
> + *   QW-1  O/S        OS context for priority management, interrupt acks
> + *   QW-2  Pool       hypervisor pool context for virtual processors 
> dispatched
> + *   QW-3  Physical   physical thread context and security context
> + */
> +#define XIVE_TM_RING_COUNT      4
> +#define XIVE_TM_RING_SIZE       0x10
> +
> +typedef struct XiveTCTX {
> +    DeviceState parent_obj;
> +
> +    CPUState    *cs;
> +    qemu_irq    output;
> +
> +    uint8_t     regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
> +} XiveTCTX;
> +
>  /*
>   * XIVE Router
>   */
> @@ -324,6 +351,7 @@ typedef struct XiveRouterClass {
>                     XiveNVT *nvt);
>      int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
>                       XiveNVT *nvt, uint8_t word_number);
> +    XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
>  } XiveRouterClass;
>  
>  void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
> @@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t 
> nvt_blk, uint32_t nvt_idx,
>                          XiveNVT *nvt);
>  int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t 
> nvt_idx,
>                            XiveNVT *nvt, uint8_t word_number);
> -
> +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
>  
>  /*
>   * XIVE END ESBs
> @@ -371,33 +399,6 @@ typedef struct XiveENDSource {
>  void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
>  void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor 
> *mon);
>  
> -/*
> - * XIVE Thread interrupt Management (TM) context
> - */
> -
> -#define TYPE_XIVE_TCTX "xive-tctx"
> -#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
> -
> -/*
> - * XIVE Thread interrupt Management register rings :
> - *
> - *   QW-0  User       event-based exception state
> - *   QW-1  O/S        OS context for priority management, interrupt acks
> - *   QW-2  Pool       hypervisor pool context for virtual processors 
> dispatched
> - *   QW-3  Physical   physical thread context and security context
> - */
> -#define XIVE_TM_RING_COUNT      4
> -#define XIVE_TM_RING_SIZE       0x10
> -
> -typedef struct XiveTCTX {
> -    DeviceState parent_obj;
> -
> -    CPUState    *cs;
> -    qemu_irq    output;
> -
> -    uint8_t     regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
> -} XiveTCTX;
> -
>  /*
>   * XIVE Thread Interrupt Management Aera (TIMA)
>   *
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index d391177ab81f..136d872f16bc 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, 
> uint8_t nvt_blk,
>      g_assert_not_reached();
>  }
>  
> +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> +{
> +    PowerPCCPU *cpu = POWERPC_CPU(cs);
> +
> +    return cpu->tctx;
> +}
> +
>  static const VMStateDescription vmstate_spapr_xive_end = {
>      .name = TYPE_SPAPR_XIVE "/end",
>      .version_id = 1,
> @@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, 
> void *data)
>      xrc->write_end = spapr_xive_write_end;
>      xrc->get_nvt = spapr_xive_get_nvt;
>      xrc->write_nvt = spapr_xive_write_nvt;
> +    xrc->get_tctx = spapr_xive_get_tctx;
>  }
>  
>  static const TypeInfo spapr_xive_info = {
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 7f567a57d25a..2e9b8efd4342 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, 
> unsigned size, bool write)
>  static void xive_tm_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
> -    PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
> -    XiveTCTX *tctx = cpu->tctx;
> +    XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
>      const XiveTmOp *xto;
>  
>      /*
> @@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
>  
>  static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
>  {
> -    PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
> -    XiveTCTX *tctx = cpu->tctx;
> +    XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
>      const XiveTmOp *xto;
>  
>      /*
> @@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t 
> nvt_blk, uint32_t nvt_idx,
>     return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
>  }
>  
> +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
> +{
> +    XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
> +
> +    return xrc->get_tctx(xrtr, cs);
> +}
> +
>  /*
>   * The thread context register words are in big-endian format.
>   */
> @@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, 
> uint8_t format,
>       */
>  
>      CPU_FOREACH(cs) {
> -        PowerPCCPU *cpu = POWERPC_CPU(cs);
> -        XiveTCTX *tctx = cpu->tctx;
> +        XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
>          int ring;
>  
>          /*