[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus error
From: |
Stefan Markovic |
Subject: |
Re: [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus errors |
Date: |
Thu, 17 Jan 2019 15:04:16 +0000 |
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim <address@hidden>
>
> Update ITU to handle bus errors.
>
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
> hw/misc/mips_itu.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
Reviewed-by: Stefan Markovic <address@hidden>
> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 5c49bdd..e8860dc 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c)
> view_pv_common_write(c);
> }
>
> +static void raise_exception(int excp)
> +{
> + current_cpu->exception_index = excp;
> + cpu_loop_exit(current_cpu);
> +}
> +
> static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
> {
> MIPSITUState *s = (MIPSITUState *)opaque;
> @@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr
> addr, unsigned size)
> ITCView view = get_itc_view(addr);
> uint64_t ret = -1;
>
> + switch (size) {
> + case 1:
> + case 2:
> + s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
> + raise_exception(EXCP_DBE);
> + return 0;
> + }
> +
> switch (view) {
> case ITCVIEW_BYPASS:
> ret = view_bypass_read(cell);
> @@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr,
> uint64_t data,
> ITCStorageCell *cell = get_cell(s, addr);
> ITCView view = get_itc_view(addr);
>
> + switch (size) {
> + case 1:
> + case 2:
> + s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
> + raise_exception(EXCP_DBE);
> + return;
> + }
> +
> switch (view) {
> case ITCVIEW_BYPASS:
> view_bypass_write(cell, data);
- [Qemu-devel] [PATCH 0/8] target/mips: Update Inter-Thread Communication Unit support, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus errors, Aleksandar Markovic, 2019/01/03
- Re: [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus errors,
Stefan Markovic <=
- [Qemu-devel] [PATCH 6/8] target/mips: Add field and R/W access to ITU control register ICR0, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 7/8] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 5/8] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 1/8] target/mips: Move comment containing summary of CP0 registers, Aleksandar Markovic, 2019/01/03