[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 04/35] target/riscv: Convert RV32I load/store ins
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v4 04/35] target/riscv: Convert RV32I load/store insns to decodetree |
Date: |
Fri, 18 Jan 2019 14:14:25 +0100 |
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
v3 -> v4:
- removed accidental argument removal
target/riscv/insn32.decode | 10 ++++++
target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 81f56c16b4..076de873c4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
# immediates:
%imm_i 20:s12
+%imm_s 25:s7 7:5
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
@@ -33,6 +34,7 @@
# Formats 32:
@i ............ ..... ... ..... ....... imm=%imm_i %rs1
%rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
address@hidden ....... ..... ..... ... ..... ....... imm=%imm_s
%rs2 %rs1
@u .................... ..... ....... imm=%imm_u
%rd
@j .................... ..... ....... imm=%imm_j
%rd
@@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
+lb ............ ..... 000 ..... 0000011 @i
+lh ............ ..... 001 ..... 0000011 @i
+lw ............ ..... 010 ..... 0000011 @i
+lbu ............ ..... 100 ..... 0000011 @i
+lhu ............ ..... 101 ..... 0000011 @i
+sb ....... ..... ..... 000 ..... 0100011 @s
+sh ....... ..... ..... 001 ..... 0100011 @s
+sw ....... ..... ..... 010 ..... 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 0347461ee6..f3b88ebb69 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
return true;
}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a)
+{
+ gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a)
+{
+ gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
+{
+ gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
+{
+ gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a)
+{
+ gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a)
+{
+ gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
+ return true;
+}
--
2.20.1
- [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 03/35] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 04/35] target/riscv: Convert RV32I load/store insns to decodetree,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v4 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18