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[Qemu-devel] [PATCH v4 22/35] target/riscv: Remove manual decoding from
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v4 22/35] target/riscv: Remove manual decoding from gen_load() |
Date: |
Fri, 18 Jan 2019 14:14:43 +0100 |
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden><Paste>
---
v3 -> v4:
- int memop -> TCGMemop memop
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++----------
target/riscv/translate.c | 6 +++--
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index eb76763fa7..fddafd9f79 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -129,34 +129,43 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool trans_lb(DisasContext *ctx, arg_lb *a)
+static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
{
- gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
return true;
}
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ return gen_load(ctx, a, MO_SB);
+}
+
static bool trans_lh(DisasContext *ctx, arg_lh *a)
{
- gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a)
{
- gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESL);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
- gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_UB);
}
static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
{
- gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUW);
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
@@ -180,14 +189,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
- gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
- gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a0e96b94a9..d0fefa8fb9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,7 +489,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx,
int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+#ifdef TARGET_RISCV64
+static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -508,6 +509,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_temp_free(t0);
tcg_temp_free(t1);
}
+#endif
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
@@ -640,7 +642,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+ gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
--
2.20.1
- Re: [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, (continued)
- [Qemu-devel] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 23/35] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 22/35] target/riscv: Remove manual decoding from gen_load(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v4 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 31/35] target/riscv: Convert @cs_2 insns to share translation functions<Paste>, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/18
- Re: [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31