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[Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx |
Date: |
Fri, 18 Jan 2019 14:57:37 +0000 |
From: Richard Henderson <address@hidden>
While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/internals.h | 15 +++++++++++++++
target/arm/helper.c | 7 +++++++
2 files changed, 22 insertions(+)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 89f3b122a49..248fdf7a3c0 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -927,4 +927,19 @@ void arm_cpu_update_vfiq(ARMCPU *cpu);
*/
ARMMMUIdx arm_mmu_idx(CPUARMState *env);
+/**
+ * arm_stage1_mmu_idx:
+ * @env: The cpu environment
+ *
+ * Return the ARMMMUIdx for the stage1 traversal for the current regime.
+ */
+#ifdef CONFIG_USER_ONLY
+static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
+{
+ return ARMMMUIdx_S1NSE0;
+}
+#else
+ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
+#endif
+
#endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 36d1832e322..35bbc7f1091 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12998,6 +12998,13 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch)
return arm_to_core_mmu_idx(arm_mmu_idx(env));
}
+#ifndef CONFIG_USER_ONLY
+ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
+{
+ return stage_1_mmu_idx(arm_mmu_idx(env));
+}
+#endif
+
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
--
2.20.1
- [Qemu-devel] [PULL 00/49] target-arm queue, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx,
Peter Maydell <=
- [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac), Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only, Peter Maydell, 2019/01/18