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[Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setti
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags |
Date: |
Fri, 18 Jan 2019 14:57:43 +0000 |
From: Richard Henderson <address@hidden>
The arm_regime_tbi{0,1} functions are replacable with the new function
by giving the lowest and highest address.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 35 -----------------------
target/arm/helper.c | 70 ++++++++++++++++-----------------------------
2 files changed, 24 insertions(+), 81 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ea9b8ec4a1e..8512ca35528 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3015,41 +3015,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
}
#endif
-#ifndef CONFIG_USER_ONLY
-/**
- * arm_regime_tbi0:
- * @env: CPUARMState
- * @mmu_idx: MMU index indicating required translation regime
- *
- * Extracts the TBI0 value from the appropriate TCR for the current EL
- *
- * Returns: the TBI0 value.
- */
-uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
-
-/**
- * arm_regime_tbi1:
- * @env: CPUARMState
- * @mmu_idx: MMU index indicating required translation regime
- *
- * Extracts the TBI1 value from the appropriate TCR for the current EL
- *
- * Returns: the TBI1 value.
- */
-uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
-#else
-/* We can't handle tagged addresses properly in user-only mode */
-static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- return 0;
-}
-
-static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- return 0;
-}
-#endif
-
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d9b580e3316..a62ce2a76e6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx
mmu_idx)
return mmu_idx;
}
-/* Returns TBI0 value for current regime el */
-uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- TCR *tcr;
- uint32_t el;
-
- /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
- * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
- */
- mmu_idx = stage_1_mmu_idx(mmu_idx);
-
- tcr = regime_tcr(env, mmu_idx);
- el = regime_el(env, mmu_idx);
-
- if (el > 1) {
- return extract64(tcr->raw_tcr, 20, 1);
- } else {
- return extract64(tcr->raw_tcr, 37, 1);
- }
-}
-
-/* Returns TBI1 value for current regime el */
-uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- TCR *tcr;
- uint32_t el;
-
- /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
- * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
- */
- mmu_idx = stage_1_mmu_idx(mmu_idx);
-
- tcr = regime_tcr(env, mmu_idx);
- el = regime_el(env, mmu_idx);
-
- if (el > 1) {
- return 0;
- } else {
- return extract64(tcr->raw_tcr, 38, 1);
- }
-}
-
/* Return the TTBR associated with this translation regime */
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn)
@@ -13054,10 +13012,30 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
*pc = env->pc;
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
- /* Get control bits for tagged addresses */
- flags = FIELD_DP32(flags, TBFLAG_A64, TBII,
- (arm_regime_tbi1(env, mmu_idx) << 1) |
- arm_regime_tbi0(env, mmu_idx));
+
+#ifndef CONFIG_USER_ONLY
+ /*
+ * Get control bits for tagged addresses. Note that the
+ * translator only uses this for instruction addresses.
+ */
+ {
+ ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
+ ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
+ int tbii, tbid;
+
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
+ if (regime_el(env, stage1) < 2) {
+ ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
+ tbid = (p1.tbi << 1) | p0.tbi;
+ tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
+ } else {
+ tbid = p0.tbi;
+ tbii = tbid & !p0.tbid;
+ }
+
+ flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
+ }
+#endif
if (cpu_isar_feature(aa64_sve, cpu)) {
int sve_el = sve_exception_el(env, current_el);
--
2.20.1
- [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max, (continued)
- [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 12/49] target/arm: Decode PAuth within disas_data_proc_1src, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 29/49] target/arm: Implement pauth_auth, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags,
Peter Maydell <=
- [Qemu-devel] [PULL 30/49] target/arm: Implement pauth_addpac, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 09/49] target/arm: Add PAuth helpers, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 32/49] target/arm: Add PAuth system registers, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET, Peter Maydell, 2019/01/18