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[Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migra
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations |
Date: |
Fri, 18 Jan 2019 14:57:54 +0000 |
From: Aaron Lindsay <address@hidden>
Because of the PMU's design, many register accesses have side effects
which are inter-related, meaning that the normal method of saving CP
registers can result in inconsistent state. These side-effects are
largely handled in pmu_op_start/finish functions which can be called
before and after the state is saved/restored. By doing this and adding
raw read/write functions for the affected registers, we avoid
migration-related inconsistencies.
Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 6 ++++--
target/arm/machine.c | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c49e0d70cbb..733cfdc5a0f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1459,11 +1459,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
.type = ARM_CP_IO,
- .readfn = pmccntr_read, .writefn = pmccntr_write, },
+ .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
+ .readfn = pmccntr_read, .writefn = pmccntr_write,
+ .raw_readfn = raw_read, .raw_writefn = raw_write, },
#endif
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
- .writefn = pmccfiltr_write,
+ .writefn = pmccfiltr_write, .raw_writefn = raw_write,
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 7a22ebc2098..b2925496148 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -620,6 +620,10 @@ static int cpu_pre_save(void *opaque)
{
ARMCPU *cpu = opaque;
+ if (!kvm_enabled()) {
+ pmu_op_start(&cpu->env);
+ }
+
if (kvm_enabled()) {
if (!write_kvmstate_to_list(cpu)) {
/* This should never fail */
@@ -641,6 +645,17 @@ static int cpu_pre_save(void *opaque)
return 0;
}
+static int cpu_post_save(void *opaque)
+{
+ ARMCPU *cpu = opaque;
+
+ if (!kvm_enabled()) {
+ pmu_op_finish(&cpu->env);
+ }
+
+ return 0;
+}
+
static int cpu_pre_load(void *opaque)
{
ARMCPU *cpu = opaque;
@@ -653,6 +668,10 @@ static int cpu_pre_load(void *opaque)
*/
env->irq_line_state = UINT32_MAX;
+ if (!kvm_enabled()) {
+ pmu_op_start(&cpu->env);
+ }
+
return 0;
}
@@ -721,6 +740,10 @@ static int cpu_post_load(void *opaque, int version_id)
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+ if (!kvm_enabled()) {
+ pmu_op_finish(&cpu->env);
+ }
+
return 0;
}
@@ -729,6 +752,7 @@ const VMStateDescription vmstate_arm_cpu = {
.version_id = 22,
.minimum_version_id = 22,
.pre_save = cpu_pre_save,
+ .post_save = cpu_post_save,
.pre_load = cpu_pre_load,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
--
2.20.1
- [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c, (continued)
- [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23], Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations,
Peter Maydell <=
- [Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial(), Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC, Peter Maydell, 2019/01/18
- Re: [Qemu-devel] [PULL 00/49] target-arm queue, no-reply, 2019/01/31