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Re: [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree |
Date: |
Sun, 20 Jan 2019 08:29:21 +1100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
> Acked-by: Alistair Francis <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Peer Adelt <address@hidden>
> ---
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvi.inc.c | 23 +++++++++++++++++++++++
> target/riscv/translate.c | 12 ------------
> 3 files changed, 25 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 1f5bf1f6f9..804b721ca5 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> sra 0100000 ..... ..... 101 ..... 0110011 @r
> or 0000000 ..... ..... 110 ..... 0110011 @r
> and 0000000 ..... ..... 111 ..... 0110011 @r
> +fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +fence_i ---- ---- ---- ----- 001 ----- 0001111
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
> b/target/riscv/insn_trans/trans_rvi.inc.c
> index 01f751650a..138a8397d9 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -318,3 +318,26 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
> return true;
> }
> #endif
> +
> +static bool trans_fence(DisasContext *ctx, arg_fence *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + /* FENCE is a full memory barrier. */
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> +#endif
> + return true;
> +}
> +
> +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + /*
> + * FENCE_I is a no-op in QEMU,
> + * however we need to end the translation block
> + */
> + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> + tcg_gen_exit_tb(NULL, 0);
> + ctx->base.is_jmp = DISAS_NORETURN;
> +#endif
> + return true;
Rebase error. You need to remove the ifdefs that were removed...
> - case OPC_RISC_FENCE:
> - if (ctx->opcode & 0x1000) {
> - /* FENCE_I is a no-op in QEMU,
> - * however we need to end the translation block */
> - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> - tcg_gen_exit_tb(NULL, 0);
> - ctx->base.is_jmp = DISAS_NORETURN;
> - } else {
> - /* FENCE is a full memory barrier. */
> - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> - }
> - break;
... from here.
r~
- [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/01/18
- Re: [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 03/35] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/18