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[Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr()
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() |
Date: |
Tue, 22 Jan 2019 10:28:54 +0100 |
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index b0f35cef14..3b3aff4803 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 53febc60b0..1f59b02c84 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx,
int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!riscv_has_ext(env, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
{
--
2.20.1
- [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/22