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[Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F insns to decod
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F insns to decodetree |
Date: |
Wed, 23 Jan 2019 10:25:16 +0100 |
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c984..6319f872ac 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index b101593ac4..b667c576d4 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
--
2.20.1
- [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, (continued)
- [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F insns to decodetree,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/01/23
- [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/23