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[Qemu-devel] [PULL 03/14] target/mips: nanoMIPS: Rename macros for extra
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 03/14] target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers |
Date: |
Fri, 25 Jan 2019 14:31:27 +0100 |
From: Aleksandar Markovic <address@hidden>
Rename macros for extracting 3-bit-coded GPR numbers, to achieve
better consistency with the nanoMIPS documentation.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 06e7bc6..2140ecd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18460,9 +18460,9 @@ enum {
/* extraction utilities */
-#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
-#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
-#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
+#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
+#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
+#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
@@ -18559,8 +18559,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt,
uint8_t count,
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
{
- int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
- int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
switch (extract32(ctx->opcode, 2, 2)) {
case NM_NOT16:
@@ -21861,9 +21861,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
- int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
- int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
- int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
+ int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
int offset;
int imm;
@@ -22026,7 +22026,7 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case NM_SB16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
gen_st(ctx, OPC_SB, rt, rs, offset);
break;
case NM_LBU16:
@@ -22045,7 +22045,7 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case NM_SH16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
gen_st(ctx, OPC_SH, rt, rs, offset);
break;
case NM_LHU16:
@@ -22100,14 +22100,14 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case NM_SW16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
- rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
+ rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
offset = extract32(ctx->opcode, 0, 4) << 2;
gen_st(ctx, OPC_SW, rt, rs, offset);
break;
case NM_SWGP16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
offset = extract32(ctx->opcode, 0, 7) << 2;
gen_st(ctx, OPC_SW, rt, 28, offset);
break;
--
2.7.4
- [Qemu-devel] [PULL 00/14] MIPS queue for January 25, 2019, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 04/14] target/mips: Correct the second argument type of cpu_supports_isa(), Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 02/14] target/mips: nanoMIPS: Remove an unused macro, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 08/14] target/mips: Add I6500 core configuration, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 01/14] target/mips: nanoMIPS: Remove duplicate macro definitions, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 09/14] MAINTAINERS: Update MIPS sections, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 11/14] tests: tcg: mips: Add two new Makefiles, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 03/14] target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 07/14] target/mips: nanoMIPS: Fix branch handling, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 13/14] qemu-doc: Add nanoMIPS ISA information, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 14/14] docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 05/14] target/mips: Extend gen_scwp() functionality to support EVA, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 06/14] disas: nanoMIPS: Amend DSP instructions related comments, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 10/14] tests: tcg: mips: Move source files to new locations, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 12/14] tests: tcg: mips: Remove old directories, Aleksandar Markovic, 2019/01/25
- Re: [Qemu-devel] [PULL 00/14] MIPS queue for January 25, 2019, Aleksandar Markovic, 2019/01/25
- Re: [Qemu-devel] [PULL 00/14] MIPS queue for January 25, 2019, Peter Maydell, 2019/01/25