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[Qemu-devel] [PATCH 19/19] target/ppc: Add support for LPCR:HEIC on POWE
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH 19/19] target/ppc: Add support for LPCR:HEIC on POWER9 |
Date: |
Mon, 28 Jan 2019 10:46:25 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
This controls whether the External Interrupt (0x500) can be
delivered to the hypervisor or not.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
---
target/ppc/excp_helper.c | 5 ++++-
target/ppc/translate_init.inc.c | 5 ++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d171a5eb6236..39bedbb11db0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -827,7 +827,10 @@ static void ppc_hw_interrupt(CPUPPCState *env)
/* External interrupt can ignore MSR:EE under some circumstances */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- if (async_deliver || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ /* HEIC blocks delivery to the hypervisor */
+ if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
+ (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
return;
}
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 7f25215f0192..63ded33ea7ea 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8823,7 +8823,10 @@ static bool cpu_has_work_POWER9(CPUState *cs)
/* External Exception */
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
- return true;
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ if (heic == 0 || !msr_hv || msr_pr) {
+ return true;
+ }
}
/* Decrementer Exception */
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
--
2.20.1
- [Qemu-devel] [PATCH 07/19] target/ppc: Make special ORs match x86 pause and don't generate on mttcg, (continued)
- [Qemu-devel] [PATCH 07/19] target/ppc: Make special ORs match x86 pause and don't generate on mttcg, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 06/19] target/ppc: Remove some #if 0'ed code, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 05/19] ppc/pnv: add XIVE support, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 13/19] target/ppc: Rename "in_pm_state" to "resume_as_sreset", Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 15/19] target/ppc: Detect erroneous condition in interrupt delivery, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 12/19] target/ppc: Disable ISA 2.06 PM instructions on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 09/19] target/ppc: Don't clobber MSR:EE on PM instructions, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 11/19] target/ppc: Move "wakeup reset" code to a separate function, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 14/19] target/ppc: Add POWER9 exception model, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 16/19] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 19/19] target/ppc: Add support for LPCR:HEIC on POWER9,
Cédric Le Goater <=
- [Qemu-devel] [PATCH 18/19] ppc/xive: Make XIVE generate the proper interrupt types, Cédric Le Goater, 2019/01/28
- [Qemu-devel] [PATCH 17/19] target/ppc: Add POWER9 external interrupt model, Cédric Le Goater, 2019/01/28