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[Qemu-devel] [PULL 06/26] exec.c: Use correct attrs in cpu_memory_rw_deb
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/26] exec.c: Use correct attrs in cpu_memory_rw_debug() |
Date: |
Mon, 28 Jan 2019 18:10:27 +0000 |
In the softmmu version of cpu_memory_rw_debug(), we ask the
CPU for the attributes to use for the virtual memory access,
and we correctly use those to identify the address space
index. However, we were not passing them in to the
address_space_write_rom() and address_space_rw() functions.
The effect of this was that a memory access from the gdbstub
to a device which had behaviour that was sensitive to the
memory attributes (such as some ARMv8M NVIC registers) was
incorrectly always performed as if non-secure, rather than
using the right security state for the CPU's current state.
Fixes: https://bugs.launchpad.net/qemu/+bug/1812091
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Stefano Garzarella <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
exec.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/exec.c b/exec.c
index 895449f9261..9557a4e523c 100644
--- a/exec.c
+++ b/exec.c
@@ -3882,12 +3882,10 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong
addr,
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write) {
address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
- MEMTXATTRS_UNSPECIFIED,
- buf, l);
+ attrs, buf, l);
} else {
address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
- MEMTXATTRS_UNSPECIFIED,
- buf, l, 0);
+ attrs, buf, l, 0);
}
len -= l;
buf += l;
--
2.20.1
- [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 01/26] target/arm: Fix validation of 32-bit address spaces for aa32, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 03/26] gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 02/26] target/arm: v8m: Ensure IDAU is respected if SAU is disabled, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 08/26] MAINTAINERS: update microbit ARM board files, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 05/26] tests/microbit-test: add TWI stub device test, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 07/26] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 09/26] target/arm: Don't clear supported PMU events when initializing PMCEID1, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 10/26] memory: add memory_region_flush_rom_device(), Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 06/26] exec.c: Use correct attrs in cpu_memory_rw_debug(),
Peter Maydell <=
- [Qemu-devel] [PULL 04/26] arm: Stub out NRF51 TWI magnetometer/accelerometer detection, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 12/26] arm: Instantiate NRF51 special NVM's and NVMC, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 11/26] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 15/26] tests/microbit-test: Check nRF51 UART functionality, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 17/26] xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 13/26] tests/libqtest: Introduce qtest_init_with_serial(), Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 18/26] aspeed/smc: fix default read value, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 21/26] aspeed/smc: snoop SPI transfers to fake dummy cycles, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 20/26] aspeed/smc: Add dummy data register, Peter Maydell, 2019/01/28
- [Qemu-devel] [PULL 19/26] aspeed/smc: define registers for all possible CS, Peter Maydell, 2019/01/28