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[Qemu-devel] [PULL 15/37] xive: add a get_tctx() method to the XiveRoute
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 15/37] xive: add a get_tctx() method to the XiveRouter |
Date: |
Mon, 4 Feb 2019 20:01:02 +1100 |
From: Cédric Le Goater <address@hidden>
It provides a mean to retrieve the XiveTCTX of a CPU. This will become
necessary with future changes which move the interrupt presenter
object pointers under the PowerPCCPU machine_data.
The PowerNV machine has an extra requirement on TIMA accesses that
this new method addresses. The machine can perform indirect loads and
stores on the TIMA on behalf of another CPU. The PIR being defined in
the controller registers, we need a way to peek in the controller
model to find the PIR value.
The XiveTCTX is moved above the XiveRouter definition to avoid forward
typedef declarations.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/spapr_xive.c | 8 ++++++
hw/intc/xive.c | 16 +++++++-----
include/hw/ppc/xive.h | 57 ++++++++++++++++++++++---------------------
3 files changed, 47 insertions(+), 34 deletions(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index d391177ab8..136d872f16 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t
nvt_blk,
g_assert_not_reached();
}
+static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ return cpu->tctx;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void
*data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
+ xrc->get_tctx = spapr_xive_get_tctx;
}
static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7f567a57d2..2e9b8efd43 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset,
unsigned size, bool write)
static void xive_tm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
- PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
- XiveTCTX *tctx = cpu->tctx;
+ XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
const XiveTmOp *xto;
/*
@@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
{
- PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
- XiveTCTX *tctx = cpu->tctx;
+ XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
const XiveTmOp *xto;
/*
@@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t
nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
+XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_tctx(xrtr, cs);
+}
+
/*
* The thread context register words are in big-endian format.
*/
@@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr,
uint8_t format,
*/
CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = cpu->tctx;
+ XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
int ring;
/*
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 5d31c801ee..ec3bb2aae4 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsrc,
uint32_t srcno,
void xive_source_set_irq(void *opaque, int srcno, int val);
+/*
+ * XIVE Thread interrupt Management (TM) context
+ */
+
+#define TYPE_XIVE_TCTX "xive-tctx"
+#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
+
+/*
+ * XIVE Thread interrupt Management register rings :
+ *
+ * QW-0 User event-based exception state
+ * QW-1 O/S OS context for priority management, interrupt acks
+ * QW-2 Pool hypervisor pool context for virtual processors dispatched
+ * QW-3 Physical physical thread context and security context
+ */
+#define XIVE_TM_RING_COUNT 4
+#define XIVE_TM_RING_SIZE 0x10
+
+typedef struct XiveTCTX {
+ DeviceState parent_obj;
+
+ CPUState *cs;
+ qemu_irq output;
+
+ uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
+} XiveTCTX;
+
/*
* XIVE Router
*/
@@ -324,6 +351,7 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
+ XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
} XiveRouterClass;
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
@@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
-
+XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
/*
* XIVE END ESBs
@@ -371,33 +399,6 @@ typedef struct XiveENDSource {
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
-/*
- * XIVE Thread interrupt Management (TM) context
- */
-
-#define TYPE_XIVE_TCTX "xive-tctx"
-#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
-
-/*
- * XIVE Thread interrupt Management register rings :
- *
- * QW-0 User event-based exception state
- * QW-1 O/S OS context for priority management, interrupt acks
- * QW-2 Pool hypervisor pool context for virtual processors dispatched
- * QW-3 Physical physical thread context and security context
- */
-#define XIVE_TM_RING_COUNT 4
-#define XIVE_TM_RING_SIZE 0x10
-
-typedef struct XiveTCTX {
- DeviceState parent_obj;
-
- CPUState *cs;
- qemu_irq output;
-
- uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
-} XiveTCTX;
-
/*
* XIVE Thread Interrupt Management Aera (TIMA)
*
--
2.20.1
- [Qemu-devel] [PULL 02/37] smbus: Add a helper to generate SPD EEPROM data, (continued)
- [Qemu-devel] [PULL 02/37] smbus: Add a helper to generate SPD EEPROM data, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 27/37] target/ppc: rework vmrg{l, h}{b, h, w} instructions to use Vsr* macros, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 11/37] spapr/vio: remove the "irq" property", David Gibson, 2019/02/04
- [Qemu-devel] [PULL 08/37] ppc/xive: fix remaining XiveFabric names, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 13/37] spapr: Forbid setting ic-mode for old machine types, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 05/37] ppc4xx: Rename ppc4xx_sdram_t in ppc440_uc.c to ppc440_sdram_t, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 19/37] ppc: remove the interrupt presenters from under PowerPCCPU, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 18/37] target/ppc: implement complete set of Vsr* macros, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 12/37] hw/ppc/spapr: Encode the SCSI channel (bus) in the SRP LUNs, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 04/37] ppc4xx: Use ram_addr_t in ppc4xx_sdram_adjust(), David Gibson, 2019/02/04
- [Qemu-devel] [PULL 15/37] xive: add a get_tctx() method to the XiveRouter,
David Gibson <=
- [Qemu-devel] [PULL 17/37] spapr: move the interrupt presenters under machine_data, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 07/37] sam460ex: Fix support for memory larger than 1GB, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 28/37] target/ppc: rework vmul{e, o}{s, u}{b, h, w} instructions to use Vsr* macros, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 06/37] ppc4xx: Pass array index to function instead of pointer into the array, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 22/37] MAINTAINERS: Merge the two e500 sections, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 23/37] spapr: Drop unused parameters from fdt building helper, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 24/37] MAINTAINERS: add myself as maintainer for Mac Old World and New World machines, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 25/37] QemuMacDrivers: update qemu_vga.ndrv to 90c488d built from submodule, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 20/37] hw/ppc: Move ppc40x_*reset() functions from ppc405_uc.c to ppc.c, David Gibson, 2019/02/04
- [Qemu-devel] [PULL 26/37] hw/ppc/spapr: Add support for "-vga cirrus", David Gibson, 2019/02/04