[Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in MemTxAttrs

[Peter Maydell]

From: Richard Henderson <address@hidden>

Caching the bit means that we will not have to re-walk the
page tables to look up the bit during translation.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: no need to OR in guarded bit status]
Signed-off-by: Peter Maydell <address@hidden>
---
 target/arm/helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 45ba678a7df..be0ec7de2a4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10577,6 +10577,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, 
target_ulong address,
     bool ttbr1_valid;
     uint64_t descaddrmask;
     bool aarch64 = arm_el_is_aa64(env, el);
+    bool guarded = false;
 
     /* TODO:
      * This code does not handle the different format TCR for VTCR_EL2.
@@ -10756,6 +10757,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, 
target_ulong address,
         }
         /* Merge in attributes from table descriptors */
         attrs |= nstable << 3; /* NS */
+        guarded = extract64(descriptor, 50, 1);  /* GP */
         if (param.hpd) {
             /* HPD disables all the table attributes except NSTable.  */
             break;
@@ -10801,6 +10803,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, 
target_ulong address,
          */
         txattrs->secure = false;
     }
+    /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.  */
+    if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
+        txattrs->target_tlb_bit0 = true;
+    }
 
     if (cacheattrs != NULL) {
         if (mmu_idx == ARMMMUIdx_S2NS) {
-- 
2.20.1