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[Qemu-devel] [PULL 23/27] target/arm: Fix set of bits kept in xregs[ARM_
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 23/27] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] |
Date: |
Thu, 14 Feb 2019 19:05:59 +0000 |
From: Richard Henderson <address@hidden>
Given that we mask bits properly on set, there is no reason
to mask them again on get. We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get. Except in the (probably normal) case in which
the set clears all of the bits.
Simplify the code in set to also clear the RES0 bits.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 28e45f0f0ba..d4b7eca30a7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12707,7 +12707,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
int i;
uint32_t fpscr;
- fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
@@ -12749,7 +12749,7 @@ static inline int vfp_exceptbits_to_host(int
target_bits)
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
int i;
- uint32_t changed;
+ uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
@@ -12758,12 +12758,13 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t
val)
/*
* We don't implement trapped exception handling, so the
- * trap enable bits are all RAZ/WI (not RES0!)
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
+ *
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
+ * (which are stored in fp_status), and the other RES0 bits
+ * in between, then we clear all of the low 16 bits.
*/
- val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE);
-
- changed = env->vfp.xregs[ARM_VFP_FPSCR];
- env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000;
env->vfp.vec_len = (val >> 16) & 7;
env->vfp.vec_stride = (val >> 20) & 3;
--
2.20.1
- [Qemu-devel] [PULL 09/27] target/arm: expose remaining CPUID registers as RAZ, (continued)
- [Qemu-devel] [PULL 09/27] target/arm: expose remaining CPUID registers as RAZ, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 10/27] linux-user/elfload: enable HWCAP_CPUID for AArch64, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 12/27] MAINTAINERS: Remove Peter Crosthwaite from various entries, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 15/27] target/arm: Rely on optimization within tcg_gen_gvec_or, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 19/27] target/arm: Remove neon min/max helpers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 14/27] hw/arm/armsse: Fix miswiring of expansion IRQs, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 13/27] hw/intc/armv7m_nvic: Allow byte accesses to SHPR1, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 11/27] arm: Allow system registers for KVM guests to be changed by QEMU code, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 22/27] target/arm: Split out flags setting from vfp compares, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 18/27] target/arm: Use tcg integer min/max primitives for neon, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 23/27] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR],
Peter Maydell <=
- [Qemu-devel] [PULL 17/27] target/arm: Use vector minmax expanders for aarch32, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 21/27] target/arm: Fix arm_cpu_dump_state vs FPSCR, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 20/27] target/arm: Fix vfp_gdb_get/set_reg vs FPSCR, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 16/27] target/arm: Use vector minmax expanders for aarch64, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 27/27] gdbstub: Send a reply to the vKill packet., Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 25/27] target/arm: Use vector operations for saturation, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 26/27] target/arm: Add missing clear_tail calls, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 24/27] target/arm: Split out FPSCR.QC to a vector field, Peter Maydell, 2019/02/14
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, no-reply, 2019/02/14
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, no-reply, 2019/02/14