Re: [Qemu-devel] [PULL 00/27] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
8fd00e6381 gdbstub: Send a reply to the vKill packet.
34aa54edfa target/arm: Add missing clear_tail calls
3846dbef44 target/arm: Use vector operations for saturation
781e41b075 target/arm: Split out FPSCR.QC to a vector field
95ef6915a6 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
d640c730a9 target/arm: Split out flags setting from vfp compares
a5563518a5 target/arm: Fix arm_cpu_dump_state vs FPSCR
6e9dcb58eb target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
bd99640853 target/arm: Remove neon min/max helpers
524621238d target/arm: Use tcg integer min/max primitives for neon
28d1ed93b1 target/arm: Use vector minmax expanders for aarch32
f8354404a2 target/arm: Use vector minmax expanders for aarch64
2fc345aa78 target/arm: Rely on optimization within tcg_gen_gvec_or
5aafc658ed hw/arm/armsse: Fix miswiring of expansion IRQs
c85153c2d9 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
4ec0189e93 MAINTAINERS: Remove Peter Crosthwaite from various entries
45ab292867 arm: Allow system registers for KVM guests to be changed by QEMU code
3382e5fb3a linux-user/elfload: enable HWCAP_CPUID for AArch64
1d9bc813e5 target/arm: expose remaining CPUID registers as RAZ
ba7bf1bc03 target/arm: expose MPIDR_EL1 to userspace
9ee0c2aab3 target/arm: expose CPUID registers to userspace
a443302926 target/arm: relax permission checks for HWCAP_CPUID registers
f59f8c968a target/arm: Restructure disas_fp_int_conv
e9d6907528 target/arm: Force result size into dp after operation
aeaa89ad82 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7124a830e4 target/arm: Implement HACR_EL2
88200603a8 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

=== OUTPUT BEGIN ===
1/27 Checking commit 88200603a8cb (target/arm: Fix CRn to be 14 for 
PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7124a830e497 (target/arm: Implement HACR_EL2)
3/27 Checking commit aeaa89ad8291 (target/arm: Fix int128_make128 lo, hi order 
in paired_cmpxchg64_be)
4/27 Checking commit e9d6907528aa (target/arm: Force result size into dp after 
operation)
5/27 Checking commit f59f8c968ae5 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit a44330292615 (target/arm: relax permission checks for 
HWCAP_CPUID registers)
7/27 Checking commit 9ee0c2aab31c (target/arm: expose CPUID registers to 
userspace)
8/27 Checking commit ba7bf1bc03e1 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1d9bc813e57b (target/arm: expose remaining CPUID registers 
as RAZ)
10/27 Checking commit 3382e5fb3a55 (linux-user/elfload: enable HWCAP_CPUID for 
AArch64)
11/27 Checking commit 45ab2928675e (arm: Allow system registers for KVM guests 
to be changed by QEMU code)
12/27 Checking commit 4ec0189e9352 (MAINTAINERS: Remove Peter Crosthwaite from 
various entries)
13/27 Checking commit c85153c2d903 (hw/intc/armv7m_nvic: Allow byte accesses to 
SHPR1)
14/27 Checking commit 5aafc658edab (hw/arm/armsse: Fix miswiring of expansion 
IRQs)
15/27 Checking commit 2fc345aa780c (target/arm: Rely on optimization within 
tcg_gen_gvec_or)
16/27 Checking commit f8354404a2f8 (target/arm: Use vector minmax expanders for 
aarch64)
17/27 Checking commit 28d1ed93b13a (target/arm: Use vector minmax expanders for 
aarch32)
18/27 Checking commit 524621238d29 (target/arm: Use tcg integer min/max 
primitives for neon)
19/27 Checking commit bd9964085387 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 6e9dcb58eb81 (target/arm: Fix vfp_gdb_get/set_reg vs 
FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+    case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;

ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+    case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;

total: 2 errors, 0 warnings, 16 lines checked

Patch 20/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

21/27 Checking commit a5563518a586 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit d640c730a965 (target/arm: Split out flags setting from 
vfp compares)
23/27 Checking commit 95ef6915a6d0 (target/arm: Fix set of bits kept in 
xregs[ARM_VFP_FPSCR])
24/27 Checking commit 781e41b075a0 (target/arm: Split out FPSCR.QC to a vector 
field)
25/27 Checking commit 3846dbef44da (target/arm: Use vector operations for 
saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+    TYPEN *d = vd, *n = vn; TYPEM *m = vm;                                 \
                                   ^

total: 1 errors, 0 warnings, 438 lines checked

Patch 25/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/27 Checking commit 34aa54edfa31 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8fd00e6381cf (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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