[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 04/43] target/ppc: Fix msync to do what hardware does
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 04/43] target/ppc: Fix msync to do what hardware does |
Date: |
Tue, 19 Feb 2019 01:30:10 +1100 |
From: BALATON Zoltan <address@hidden>
According to BookE docs, invalid bits (while undefined behaviour) should
not raise exception but be ignored. This seems to be implementation
dependent though and QEMU currently does what e500 CPUs do and raise
exception for invalid bits. Unfortunately some versions of libstdc++
(and so all programs compiled with it) have lwsync on PPC440 which is
invalid but on real hardware it's just executed as msync ignoring the
invalid bits (maybe that's why it got undetected) but they fail on QEMU.
This patch changes invalid mask of msync to allow these programs to run
but keep generating exception on e500 cores to follow what hardware does.
Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e169c43643..5429ceb1ab 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6476,7 +6476,12 @@ static void gen_mbar(DisasContext *ctx)
/* msync replaces sync on 440 */
static void gen_msync_4xx(DisasContext *ctx)
{
- /* interpreted as no-op */
+ /* Only e500 seems to treat reserved bits as invalid */
+ if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
+ (ctx->opcode & 0x03FFF801)) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+ }
+ /* otherwise interpreted as no-op */
}
/* icbt */
@@ -7054,11 +7059,11 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01,
PPC_WRTEE),
GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
PPC_BOOKE, PPC2_BOOKE206),
-GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
+GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
- PPC_440_SPEC),
+ PPC_440_SPEC),
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
--
2.20.1
- [Qemu-devel] [PULL 00/43] ppc-for-4.0 queue 20190219, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 01/43] hw/ppc/prep: Drop useless inclusion of "hw/i386/pc.h", David Gibson, 2019/02/18
- [Qemu-devel] [PULL 03/43] target/ppc: Enable reporting of SPRs to GDB, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 05/43] spapr_pci: Fix interrupt leak in rtas_ibm_change_msi() error path, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 02/43] spapr: Rename xics to intc in interrupt controller agnostic code, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 04/43] target/ppc: Fix msync to do what hardware does,
David Gibson <=
- [Qemu-devel] [PULL 07/43] spapr: Disallow unsupported kernel-irqchip settings, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 06/43] cuda: decrease time delay before raising VIA SR interrupt and remove fast path, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 08/43] mac_newworld: change default NIC to sungem for mac99 machine, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 10/43] ppc: fix crash during branch stepping, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 09/43] target/ppc: Remove some #if 0'ed code, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 11/43] xive: Only set source type for LSIs, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 16/43] spapr/irq: remove the XICS offset adjustment, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 17/43] xics: Explicitely call KVM ICP methods from the common code, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 13/43] target/ppc: Disable ISA 2.06 PM instructions on POWER9, David Gibson, 2019/02/18
- [Qemu-devel] [PULL 19/43] xics: Handle KVM ICP realize from the common code, David Gibson, 2019/02/18