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Re: [Qemu-devel] Testing sysbus devices

From: Stephen Checkoway
Subject: Re: [Qemu-devel] Testing sysbus devices
Date: Fri, 22 Feb 2019 08:31:04 -0500

> On Feb 22, 2019, at 02:42, Markus Armbruster <address@hidden> wrote:
> Awesome.  The magic setup code in hw/i386/pc_sysfw.c will happily create
> any size that's a multiple of 4KiB.  The current sizes are 128KiB
> writable (power of two, good) and 2MiB - 128KiB for read-only (very much
> not a power of two, possibly bad).

As far as I can tell, the code I'm touching does not even compile by default 
for the i386 which only supports flash chips with the Intel command set 
hw/block/pflash_cfi01.c and not the flash chips with the AMD command set 

> Can you tell us a bit more about what exactly can go wrong?

I don't know anything at all about the pflash_cfi01.c code. So if it's working 
now, then it's probably fine.

If you had been using pflash_cfi02.c, the problem would be that it has support 
for mapping the chip at multiple, consecutive locations (I'm not sure why 
that's part of the device itself and not something setup by code that's using 
the device). So device accesses mask offsets in the read and write functions by 
pfl->chip_len - 1 (here 
<https://github.com/qemu/qemu/blob/master/hw/block/pflash_cfi02.c#L154> and 
here <https://github.com/qemu/qemu/blob/master/hw/block/pflash_cfi02.c#L279>). 
If the chip size isn't a power of two, this breaks.

Stephen Checkoway

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