Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

[Richard Henderson]

On 2/23/19 11:57 PM, Amed Magdy wrote:
> Thank you for your review and feedback, Richard.
> As Eric mentioned, this is the first time contribution. I have been exploring
> Qemu for some time and try to understand main flow, internals, ..etc.
> 
>>  You cannot manipulate env like this during translation.
> 
>>  Neither the write to env->pc_next nor the read from env->pending_rvc here 
>>will
>>  be in any synchronization with the execution of write_misa. 
>  
> Does this applies for translated code in a single translation block only or 
> for
> different TBs also ?

All of the time this will not work.

> So should I manipulate "env" from translation context through helpers only ?
> for example:
> 
> TCGv temp;
> tcg_gen_movi_tl(temp, ctx->pc_succ_insn);
> gen_helper_next_pc(cpu_env, temp);
> 
> while the helper function definition like that:
> void helper_next_pc(CPURISCVState *env, target_ulong pc_next)
> {
>     env->pc_next = pc_next;
> }

This is a correct way to write pc_next.  (Although I still don't understand why
you need it.)

> and the same to read "env->pending_rvc"

No, you cannot read pending_rvc this way.  You would need to incorporate
pending_rvc into the flags set by cpu_get_tb_cpu_state.  (Although I still
don't understand why you need it.)

> I'm thinking of a way to add 'C' extension at run time through waiting the
> correct aligned instruction, which I believe it might be after branch 
> something
> quite similar to switching between ARM and THUMB states in ARM, for misa 'RVC'
> enable to take effect since it will be no possibility to check alignment with
> 'C' extension.

It seems to me that the C extension can be enabled at any point, since if C is
off, you know that the next insn is aligned modulo 4.

It is only if the C extension is enabled, and you want to disable it, that is
when we must check to see if the next insn is aligned mod 4.  It is trivial to
arrange for a particular instruction to be aligned, via assembler directives.
So it seems silly to make the definition of the csr write to misa any more
complicated than it is.

You are right that the existing code is broken, in that it is checking the
alignment of the host PC and not the guest PC.  However, I see no reason to
introduce a new "pc_next" field when we already update the pc field ...

> static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
>                        int csr)
> {
>     TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
>     source1 = tcg_temp_new();
>     csr_store = tcg_temp_new();
>     dest = tcg_temp_new();
>     rs1_pass = tcg_temp_new();
>     imm_rs1 = tcg_temp_new();
>     gen_get_gpr(source1, rs1);
>     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);

... here.

So as far as I can see, the only thing that needs fixing is GETPC.


r~


diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 960d2b0aa9..8726ef802e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -370,10 +370,11 @@ static int write_misa(CPURISCVState *env, int csrno,
target_ulong val)
         val &= ~RVD;
     }

-    /* Suppress 'C' if next instruction is not aligned
-     * TODO: this should check next_pc
+    /*
+     * Suppress 'C' if next instruction is not aligned.
+     * We updated env->pc to the next insn in the translator.
      */
-    if ((val & RVC) && (GETPC() & ~3) != 0) {
+    if ((val & RVC) && (env->pc & ~3) != 0) {
         val &= ~RVC;
     }