Re: [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH

[Richard Henderson]

On 2/26/19 4:23 AM, Mateja Marjanovic wrote:
> +    } else if (rd == rt) {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 16) - 1;
> +        uint64_t mask1 = mask0 << 16;
> +        uint64_t mask2 = mask1 << 16;
> +        uint64_t mask3 = (mask2 << 16) | mask0;
> +
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +
> +        tcg_gen_andi_i64(cpu_gpr[rt], cpu_gpr[rt], mask3);
> +        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
> +        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +
> +        tcg_gen_andi_i64(cpu_mmr[rt], cpu_mmr[rt], mask3);
> +        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> +        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
> +
> +        tcg_temp_free(t0);
> +        tcg_temp_free(t1);
> +    } else {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 16) - 1;
> +        uint64_t mask1 = mask0 << 16;
> +        uint64_t mask2 = mask1 << 16;
> +        uint64_t mask3 = mask2 << 16;
> +
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> +        tcg_gen_shli_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> +        tcg_gen_or_i64(t0, t0, t1);
> +
> +        tcg_gen_mov_i64(cpu_gpr[rd], t0);
> +
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
> +        tcg_gen_shli_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> +        tcg_gen_or_i64(t0, t0, t1);
> +
> +        tcg_gen_mov_i64(cpu_mmr[rd], t0);
> +
> +        tcg_temp_free(t0);
> +        tcg_temp_free(t1);
> +    }

The code for rd != rt will work just fine for rd == rt.
Why are you doubling the amount of code you are writing?


r~