Re: [Qemu-devel] [PATCH 2/2] target/arm: Implement ARMv8.0-PredRes

[Peter Maydell]

On Wed, 20 Feb 2019 at 23:50, Richard Henderson
<address@hidden> wrote:
>
> This is named "Execution and Data prediction restriction instructions"
> within the ARMv8.5 manual, and given the name "PredRes" by binutils.

The official name is v8.0-PredInv.
(You can see this used in the xml descriptions for the new insns, eg:
https://developer.arm.com/docs/ddi0595/b/aarch64-system-instructions/cfp-rctx )


>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/cpu.h    | 11 ++++++++++
>  target/arm/cpu.c    |  1 +
>  target/arm/cpu64.c  |  2 ++
>  target/arm/helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 63 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 76d6a73c0e..202ff1f1ea 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1074,6 +1074,7 @@ void pmu_init(ARMCPU *cpu);
>  #define SCTLR_UMA     (1U << 9) /* v8 onward, AArch64 only */
>  #define SCTLR_F       (1U << 10) /* up to v6 */
>  #define SCTLR_SW      (1U << 10) /* v7, RES0 in v8 */
> +#define SCTLR_EnRCTX  (1U << 10) /* in v8.0-specres */

You should delete the "RES0 in v8" from the preceding comment
(and update the feature name to v8.0-PredInv).

>  #define SCTLR_Z       (1U << 11) /* in v7, RES1 in v8 */
>  #define SCTLR_EOS     (1U << 11) /* v8.5-ExS */
>  #define SCTLR_I       (1U << 12)

> +
> +    /* All v8.0-a cpus support aarch64.  */

True, but why is it relevant here ?

> +    if (cpu_isar_feature(aa64_specres, cpu)) {
> +        define_arm_cp_regs(cpu, specres_reginfo);
> +    }
>  }
>
>  void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
> --
> 2.17.2

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM