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[Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarc
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64 |
Date: |
Thu, 28 Feb 2019 11:08:32 +0000 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 5 ++++
target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3e545a2b146..8f52914649d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3404,6 +3404,11 @@ static inline bool isar_feature_aa64_dp(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
}
+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
+}
+
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c56e878787c..d3c8eaf0893 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10917,9 +10917,29 @@ static void disas_simd_3same_float(DisasContext *s,
uint32_t insn)
if (!fp_access_check(s)) {
return;
}
-
handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
return;
+
+ case 0x1d: /* FMLAL */
+ case 0x3d: /* FMLSL */
+ case 0x59: /* FMLAL2 */
+ case 0x79: /* FMLSL2 */
+ if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+ if (fp_access_check(s)) {
+ int is_s = extract32(insn, 23, 1);
+ int is_2 = extract32(insn, 29, 1);
+ int data = (is_2 << 1) | is_s;
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), cpu_env,
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ data, gen_helper_gvec_fmlal_a64);
+ }
+ return;
+
default:
unallocated_encoding(s);
return;
@@ -12739,6 +12759,17 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
}
is_fp = 2;
break;
+ case 0x00: /* FMLAL */
+ case 0x04: /* FMLSL */
+ case 0x18: /* FMLAL2 */
+ case 0x1c: /* FMLSL2 */
+ if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+ size = MO_16;
+ /* is_fp, but we pass cpu_env not fp_status. */
+ break;
default:
unallocated_encoding(s);
return;
@@ -12849,6 +12880,22 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
tcg_temp_free_ptr(fpst);
}
return;
+
+ case 0x00: /* FMLAL */
+ case 0x04: /* FMLSL */
+ case 0x18: /* FMLAL2 */
+ case 0x1c: /* FMLSL2 */
+ {
+ int is_s = extract32(opcode, 2, 1);
+ int is_2 = u;
+ int data = (index << 2) | (is_2 << 1) | is_s;
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), cpu_env,
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ data, gen_helper_gvec_fmlal_idx_a64);
+ }
+ return;
}
if (size == 3) {
--
2.20.1
- [Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize, (continued)
- [Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 01/16] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 06/16] hw/arm/iotkit-sysctl: Add SSE-200 registers, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 02/16] hw/arm/armsse: Wire up the MHUs, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 09/16] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 08/16] hw/arm/armsse: Unify init-svtor and cpuwait handling, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 10/16] target/arm: Gate "miscellaneous FP" insns by ID register field, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 11/16] Revert "arm: Allow system registers for KVM guests to be changed by QEMU code", Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 12/16] target/arm: Add helpers for FMLAL, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64,
Peter Maydell <=
- [Qemu-devel] [PULL 15/16] target/arm: Enable ARMv8.2-FHM for -cpu max, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32, Peter Maydell, 2019/02/28
- [Qemu-devel] [PULL 16/16] linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT, Peter Maydell, 2019/02/28
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, no-reply, 2019/02/28
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2019/02/28