Re: [Qemu-devel] x86 segment limits enforcement with TCG

[Richard Henderson]

On 2/28/19 9:18 AM, Stephen Checkoway wrote:
> I wonder if it would make sense to maintain a small cache of TLBs. The
> majority of cases are likely to involving setting segment registers to one
> of a handful of segments (e.g., setting es to ds or ss). So it might be nice
> to avoid the flushes entirely.
Hmm.

The straight-forward approach to this would change the mapping between segment
and mmu index, which would need to force a new translation (since mmu indexes
are built into the generated code as constants).  It would be easy for this
scheme to generate too many translations and slow down the system as a whole.

However, since the change to dynamic tlbs, the actual tlb is now a pointer.  So
it might not be out of the question to simply swap TLB contents around when
changing segment registers.  All you would need is N+1 tlbs to support the
(easy?) case of es swapping.

With some additional work in cputlb, it might even be possible to have
different mmu indexes share the same backing tlb.  This would be tricky to
manage during a tlb resize, but perhaps not impossible.

Emilio, do you have any thoughts here?


> I agree that the vast majority of x86 instructions access at most one
> segment, but off-hand, I can think of a handful that access two:
> 
> - movs 
> - cmps
> - push r/m32
> - pop r/m32
> - call m32
> - call m16:m32
> 
> I'm not sure if there are others.

Sure, but my point is that we're certainly talking about 10's not 1000's, which
is where we were when talking about every memory operation for every x86
instruction.


r~