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Re: [Qemu-devel] [PATCH v2 03/15] ppc/pnv: lpc: fix OPB address ranges
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH v2 03/15] ppc/pnv: lpc: fix OPB address ranges |
Date: |
Fri, 8 Mar 2019 10:59:09 +1100 |
User-agent: |
Mutt/1.11.3 (2019-02-01) |
On Thu, Mar 07, 2019 at 11:35:36PM +0100, Cédric Le Goater wrote:
> The PowerNV LPC Controller exposes different sets of registers for
> each of the functional units it encompasses, among which the OPB
> (On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
> Controller.
>
> The mapping addresses of each register range are correct but the sizes
> are too large. Fix the sizes and define the OPB Arbitrer range to fill
> the gap between the OPB Master registers and the LPC HOST Controller
> registers.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Applied, thanks.
> ---
>
> Changes in v2 :
>
> - wrote a commit log
>
> hw/ppc/pnv_lpc.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index 9b18ce55e391..547be609cafe 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -89,10 +89,11 @@ enum {
> #define LPC_FW_OPB_SIZE 0x10000000
>
> #define LPC_OPB_REGS_OPB_ADDR 0xc0010000
> -#define LPC_OPB_REGS_OPB_SIZE 0x00002000
> +#define LPC_OPB_REGS_OPB_SIZE 0x00000060
> +#define LPC_OPB_REGS_OPBA_ADDR 0xc0011000
> +#define LPC_OPB_REGS_OPBA_SIZE 0x00000008
> #define LPC_HC_REGS_OPB_ADDR 0xc0012000
> -#define LPC_HC_REGS_OPB_SIZE 0x00001000
> -
> +#define LPC_HC_REGS_OPB_SIZE 0x00000100
>
> static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int
> xscom_offset)
> {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH v2 07/15] ppc/pnv: add SerIRQ routing registers, (continued)
- [Qemu-devel] [PATCH v2 11/15] ppc/pnv: POWER9 XSCOM quad support, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 01/15] ppc/pnv: add a PSI bridge class model, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 06/15] ppc/pnv: add a LPC Controller model for POWER9, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 15/15] target/ppc: add HV support for POWER9, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 03/15] ppc/pnv: lpc: fix OPB address ranges, Cédric Le Goater, 2019/03/07
- Re: [Qemu-devel] [PATCH v2 03/15] ppc/pnv: lpc: fix OPB address ranges,
David Gibson <=
- [Qemu-devel] [PATCH v2 10/15] ppc/pnv: extend XSCOM core support for POWER9, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 14/15] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 05/15] ppc/pnv: add a 'dt_isa_nodename' to the chip, Cédric Le Goater, 2019/03/07
- [Qemu-devel] [PATCH v2 08/15] ppc/pnv: add a OCC model class, Cédric Le Goater, 2019/03/07